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shader: lower whole-wave OR scans to subgroup reductions
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@@ -45695,60 +45695,75 @@ TestCase ImageAtomicGlc0DoesNotReturnOldValue() {
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return test;
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}
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void AppendWave64Minimum(std::vector<u32> &code) {
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// Reduces v13 into v0 with V_MIN_U32/S_MIN_U32 or, for bitwise_or, V_OR_B32/S_OR_B32.
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void AppendWave64Reduction(std::vector<u32> &code, bool bitwise_or) {
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const u32 vector_op = bitwise_or ? 0x1cu : 0x13u;
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code.insert(code.end(), {EncodeSop1(0x04, 24, 126), // Save contributing lanes.
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EncodeSop1(0x28, 106, 126)});
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AppendVop3(&code, 0x101, 13, 193, Vgpr(13), 24); // Inactive lanes contribute UINT_MAX.
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// Inactive lanes contribute the identity: 0 for OR, UINT_MAX for the minimum.
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AppendVop3(&code, 0x101, 13, bitwise_or ? 128u : 193u, Vgpr(13), 24);
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for (u32 shift : {1u, 2u, 4u, 8u}) {
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code.push_back(EncodeVop2(0x13, 13, 250, 13));
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code.push_back(EncodeVop2(vector_op, 13, 250, 13));
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code.push_back(EncodeVop2Dpp(13, 0x110u + shift));
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}
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// Exact RDNA2 wave64 reduction from PS 964747887d898821, PCs 0x224..0x244.
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// RDNA2 wave64 reduction from PS 964747887d898821, PCs 0x224..0x244.
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code.insert(code.end(), {0xd778100cu, 0x0305830du,
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EncodeVop2(0x13, 13, Vgpr(13), 12), EncodeSop1(0x04, 126, 106),
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EncodeVop2(vector_op, 13, Vgpr(13), 12), EncodeSop1(0x04, 126, 106),
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0xd7600006u, 0x00013f0du, 0xd7600007u, 0x00017f0du,
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EncodeSop2(0x07, 8, 6, 7), EncodeVop1(0x01, 0, 8)});
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EncodeSop2(bitwise_or ? 0x10u : 0x07u, 8, 6, 7), EncodeVop1(0x01, 0, 8)});
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}
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GraphicsCase GraphicsSparseWaveMinimum() {
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std::vector<ShaderOpcode> Wave64ReductionOpcodes(bool bitwise_or) {
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using O = ShaderOpcode;
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return {bitwise_or ? O::V_OR_B32 : O::V_MIN_U32, O::V_PERMLANEX16_B32,
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O::V_READLANE_B32, bitwise_or ? O::S_OR_B32 : O::S_MIN_U32};
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}
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GraphicsCase GraphicsSparseWaveReduction(bool bitwise_or) {
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GraphicsCase test;
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test.name = "GraphicsSparseWaveMinimum";
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test.name = bitwise_or ? "GraphicsSparseWaveOr" : "GraphicsSparseWaveMinimum";
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auto &code = test.fragment_code;
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code = {EncodeVintrp(0x02, 13, 0, 0, 2)};
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AppendWave64Minimum(code);
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AppendWave64Reduction(code, bitwise_or);
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code.insert(code.end(), {EncodeExp0(0x00, 0xf), EncodeExp1(0, 0, 0, 0)});
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AppendEnd(&code);
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test.pixel_interpolator_settings = {0x00000400u};
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test.expected_pixel = {0x3e800000u, 0x3e800000u, 0x3e800000u, 0x3e800000u};
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test.opcodes = {ShaderOpcode::V_MIN_U32, ShaderOpcode::V_PERMLANEX16_B32,
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ShaderOpcode::V_READLANE_B32, ShaderOpcode::S_MIN_U32};
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test.opcodes = Wave64ReductionOpcodes(bitwise_or);
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return test;
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}
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TestCase ComputeWave64Minimum(bool masked) {
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TestCase ComputeWave64Reduction(bool masked, bool bitwise_or) {
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TestCase test;
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test.name = masked ? "ComputeWave64MinimumMasked" : "ComputeWave64Minimum";
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auto &code = test.code;
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code = {EncodeVop2(0x1a, 20, InlineU32(2), 0)};
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AppendVMovU32(&code, 13, 100);
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code.push_back(EncodeVop2(0x26, 13, Vgpr(13), 0)); // 100 - lane: minimum is in the upper half.
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if (bitwise_or) {
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// Lane i contributes bit i / 4, so each half supplies its own byte of 0xffff.
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test.name = "ComputeWave64Or";
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test.expected.assign(64, 0xffffu);
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code.push_back(EncodeVop2(0x16, 13, InlineU32(2), 0));
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AppendVop3(&code, 0x11a, 13, Vgpr(13), InlineU32(1));
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} else {
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test.name = masked ? "ComputeWave64MinimumMasked" : "ComputeWave64Minimum";
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test.expected.assign(64, masked ? 38u : 37u);
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AppendVMovU32(&code, 13, 100);
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code.push_back(EncodeVop2(0x26, 13, Vgpr(13), 0)); // 100 - lane: minimum is in the upper half.
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}
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if (masked) {
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AppendSMovLiteral(&code, 126, 0xfffffffeu);
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AppendSMovLiteral(&code, 127, 0x7fffffffu);
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}
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AppendWave64Minimum(code);
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AppendWave64Reduction(code, bitwise_or);
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AppendBufferStoreDword(&code, 0, 20);
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AppendEnd(&code);
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test.initial.assign(64, 0xa5a5a5a5u);
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test.expected.assign(64, masked ? 38u : 37u);
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if (masked) test.expected.front() = test.expected.back() = 0xa5a5a5a5u;
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test.compute_info.threads_num[0] = 64;
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test.compute_info.threads_num[1] = test.compute_info.threads_num[2] = 1;
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test.compute_info.thread_ids_num = 1;
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test.compute_info.wave_size = 64;
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test.has_compute_info = true;
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test.opcodes = {ShaderOpcode::V_MIN_U32, ShaderOpcode::V_PERMLANEX16_B32,
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ShaderOpcode::V_READLANE_B32, ShaderOpcode::S_MIN_U32};
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test.opcodes = Wave64ReductionOpcodes(bitwise_or);
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return test;
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}
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@@ -46627,8 +46642,9 @@ std::vector<TestCase> MakeCases() {
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cases.push_back(VectorDppMirrorAndRotate(64));
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cases.push_back(VectorReadFirstLaneExecMasks(32));
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cases.push_back(VectorReadFirstLaneExecMasks(64));
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cases.push_back(ComputeWave64Minimum(false));
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cases.push_back(ComputeWave64Minimum(true));
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cases.push_back(ComputeWave64Reduction(false, false));
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cases.push_back(ComputeWave64Reduction(true, false));
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cases.push_back(ComputeWave64Reduction(false, true));
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AddCase(VectorDppBankMaskPreservesDestination);
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for (const bool row_shift : {false, true})
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for (const bool bound_ctrl : {false, true})
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@@ -47072,7 +47088,8 @@ std::vector<TestCase> MakeCases() {
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std::vector<GraphicsCase> MakeGraphicsCases() {
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return {
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GraphicsSparseWaveMinimum(),
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GraphicsSparseWaveReduction(false),
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GraphicsSparseWaveReduction(true),
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GraphicsInterpolationExport(),
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GraphicsPositionWExport(),
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GraphicsPackedHalfCentroid(),
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@@ -53177,9 +53194,11 @@ int main(int argc, char **argv) {
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}
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if (argc == 2 && std::strcmp(argv[1], "--dpp-only") == 0) {
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VulkanHarness vulkan;
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RunGraphicsCase(&vulkan, GraphicsSparseWaveMinimum());
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RunCase(&vulkan, ComputeWave64Minimum(false));
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RunCase(&vulkan, ComputeWave64Minimum(true));
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RunGraphicsCase(&vulkan, GraphicsSparseWaveReduction(false));
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RunGraphicsCase(&vulkan, GraphicsSparseWaveReduction(true));
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RunCase(&vulkan, ComputeWave64Reduction(false, false));
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RunCase(&vulkan, ComputeWave64Reduction(true, false));
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RunCase(&vulkan, ComputeWave64Reduction(false, true));
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RunCase(&vulkan, VectorDpp8Captured(false));
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for (const u32 wave_size : {32u, 64u})
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for (const bool fi : {false, true})
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