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shader: V_MUL_LO_U16
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@@ -300,6 +300,7 @@ enum class Opcode {
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V_SUBREV_NC_U32,
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V_SUBREV_NC_U32,
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V_ADD_NC_U16,
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V_ADD_NC_U16,
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V_SUB_NC_U16,
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V_SUB_NC_U16,
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V_MUL_LO_U16,
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V_MAX_U16,
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V_MAX_U16,
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V_MAX_I16,
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V_MAX_I16,
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V_MIN_U16,
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V_MIN_U16,
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@@ -295,6 +295,7 @@ constexpr OpcodeMap VOP3_OPCODE_LIST[] = {
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{0x300u, Opcode::V_LSHRREV_B64},
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{0x300u, Opcode::V_LSHRREV_B64},
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{0x303u, Opcode::V_ADD_NC_U16},
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{0x303u, Opcode::V_ADD_NC_U16},
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{0x304u, Opcode::V_SUB_NC_U16},
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{0x304u, Opcode::V_SUB_NC_U16},
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{0x305u, Opcode::V_MUL_LO_U16},
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{0x307u, Opcode::V_LSHRREV_B16},
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{0x307u, Opcode::V_LSHRREV_B16},
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{0x308u, Opcode::V_ASHRREV_I16},
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{0x308u, Opcode::V_ASHRREV_I16},
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{0x309u, Opcode::V_MAX_U16},
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{0x309u, Opcode::V_MAX_U16},
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@@ -430,6 +431,7 @@ bool IsNativeVop3B16BinaryOpcode(Opcode opcode) {
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switch (opcode) {
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switch (opcode) {
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case Opcode::V_ADD_NC_U16:
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case Opcode::V_ADD_NC_U16:
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case Opcode::V_SUB_NC_U16:
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case Opcode::V_SUB_NC_U16:
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case Opcode::V_MUL_LO_U16:
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case Opcode::V_MAX_U16:
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case Opcode::V_MAX_U16:
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case Opcode::V_MAX_I16:
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case Opcode::V_MAX_I16:
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case Opcode::V_MIN_U16:
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case Opcode::V_MIN_U16:
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@@ -1174,6 +1176,7 @@ uint32_t NativeVop3SourceCount(Opcode opcode) {
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case Opcode::V_MUL_I32_I24:
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case Opcode::V_MUL_I32_I24:
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case Opcode::V_ADD_NC_U16:
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case Opcode::V_ADD_NC_U16:
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case Opcode::V_SUB_NC_U16:
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case Opcode::V_SUB_NC_U16:
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case Opcode::V_MUL_LO_U16:
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case Opcode::V_MAX_U16:
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case Opcode::V_MAX_U16:
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case Opcode::V_MAX_I16:
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case Opcode::V_MAX_I16:
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case Opcode::V_MIN_U16:
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case Opcode::V_MIN_U16:
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@@ -324,6 +324,7 @@ bool Translator::EmitVector(const Decoder::Instruction& inst) {
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case O::V_ADD_NC_I16: return Integer16Binary(inst, IR::ValueOpcode::IAdd32, false);
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case O::V_ADD_NC_I16: return Integer16Binary(inst, IR::ValueOpcode::IAdd32, false);
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case O::V_SUB_NC_U16:
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case O::V_SUB_NC_U16:
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case O::V_SUB_NC_I16: return Integer16Binary(inst, IR::ValueOpcode::ISub32, false);
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case O::V_SUB_NC_I16: return Integer16Binary(inst, IR::ValueOpcode::ISub32, false);
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case O::V_MUL_LO_U16: return Integer16Binary(inst, IR::ValueOpcode::IMul32, false);
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case O::V_MED3_I16: return V_MED3_I16(inst);
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case O::V_MED3_I16: return V_MED3_I16(inst);
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case O::V_MIN_I16: return Integer16Binary(inst, IR::ValueOpcode::SMin32, true);
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case O::V_MIN_I16: return Integer16Binary(inst, IR::ValueOpcode::SMin32, true);
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case O::V_MAX_I16: return Integer16Binary(inst, IR::ValueOpcode::SMax32, true);
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case O::V_MAX_I16: return Integer16Binary(inst, IR::ValueOpcode::SMax32, true);
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@@ -18159,6 +18159,51 @@ TestCase Vop3CvtPkI16I32Captured() {
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return test;
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return test;
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}
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}
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TestCase Vop3MulLoU16CapturedAndSelectors() {
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using O = ShaderOpcode;
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TestCase test;
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test.name = "Vop3MulLoU16CapturedAndSelectors";
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// Distinct runtime halves expose source selection and prevent constant folding.
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test.initial = {0x00138001u, 0x0005ffffu, 0xffffffffu};
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test.expected = {0x00138001u, 0x0005ffffu, 0xffffffffu,
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0xa5a57fffu, 0xa5a5ffedu, 0xa5a58005u, 0xa5a5005fu,
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0x7fff1234u, 0xffed1234u, 0x80051234u, 0x005f1234u,
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0xffff0001u, 0x00231234u};
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auto &code = test.code;
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AppendBufferLoadDword(&code, 12, 30);
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AppendVMovU32(&code, 30, 4);
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AppendBufferLoadDword(&code, 24, 30);
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u32 output = 3;
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for (u32 selectors : {0u, 1u, 2u, 3u, 8u, 9u, 10u, 11u}) {
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AppendVMovLiteral(&code, 2, 0xa5a51234u);
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if (selectors == 8u) {
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code.push_back(0xd7054002u);
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code.push_back(0x0002310cu); // Captured v_mul_lo_u16 v2.hi, v12.lo, v24.lo.
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} else {
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AppendVop3(&code, 0x305, 2, Vgpr(12), Vgpr(24), 0, 0, selectors);
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}
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AppendStoreVgpr(&code, 2, output++);
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}
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// 0xffff * 0xffff wraps to 1; aliasing preserves the original high half.
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AppendVMovU32(&code, 30, 8);
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AppendBufferLoadDword(&code, 12, 30);
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AppendVop3(&code, 0x305, 12, Vgpr(12), Vgpr(12), 0, 0, 1);
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AppendStoreVgpr(&code, 12, output++);
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AppendVMovLiteral(&code, 2, 0xa5a51234u);
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AppendVop3(&code, 0x305, 2, 255, Vgpr(24), 0, 0, 11);
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code.push_back(0x0007deadu); // Select literal high half: 7 * 5 = 35.
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AppendStoreVgpr(&code, 2, output);
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AppendEnd(&code);
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test.opcodes = {O::V_MOV_B32, O::BUFFER_LOAD_DWORD, O::V_MUL_LO_U16,
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O::BUFFER_STORE_DWORD, O::S_ENDPGM};
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test.decoded_counts = {{"V_MUL_LO_U16", 10}};
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test.required_spirv = {"OpIMul"};
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return test;
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}
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TestCase Vop3Med3I16Captured() {
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TestCase Vop3Med3I16Captured() {
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using O = ShaderOpcode;
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using O = ShaderOpcode;
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@@ -26909,6 +26954,7 @@ std::vector<TestCase> MakeCases() {
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AddCase(Vop2SdwaLshrrevCapturedByte1Source);
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AddCase(Vop2SdwaLshrrevCapturedByte1Source);
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AddCase(Vop2SdwaSubNcPreservesByteAndWordDestinations);
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AddCase(Vop2SdwaSubNcPreservesByteAndWordDestinations);
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AddCase(Vop3CvtPkI16I32Captured);
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AddCase(Vop3CvtPkI16I32Captured);
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AddCase(Vop3MulLoU16CapturedAndSelectors);
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AddCase(Vop3Med3I16Captured);
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AddCase(Vop3Med3I16Captured);
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AddCase(Vop2SdwaMinU32PreservesWordDestination);
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AddCase(Vop2SdwaMinU32PreservesWordDestination);
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AddCase(VectorShiftCountsMaskLowBits);
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AddCase(VectorShiftCountsMaskLowBits);
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@@ -31913,6 +31959,11 @@ int main(int argc, char **argv) {
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RunCase(&vulkan, Vop3Med3I16Captured());
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RunCase(&vulkan, Vop3Med3I16Captured());
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return 0;
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return 0;
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}
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}
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if (argc == 2 && std::strcmp(argv[1], "--mul-lo-u16-only") == 0) {
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VulkanHarness vulkan;
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RunCase(&vulkan, Vop3MulLoU16CapturedAndSelectors());
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return 0;
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}
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if (argc == 2 && std::strcmp(argv[1], "--waitcnt-depctr-only") == 0) {
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if (argc == 2 && std::strcmp(argv[1], "--waitcnt-depctr-only") == 0) {
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VulkanHarness vulkan;
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VulkanHarness vulkan;
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RunCase(&vulkan, ScalarWaitcntDepctrCapturedVmVsrc());
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RunCase(&vulkan, ScalarWaitcntDepctrCapturedVmVsrc());
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