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shader: implement DS_INC_U32 and DS_DEC_U32 (#790)
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fc86509aac
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@@ -86,6 +86,7 @@ constexpr MemoryOpcodeInfo FLAT_OPCODE_LIST[] = {
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constexpr MemoryOpcodeInfo DS_OPCODE_LIST[] = {
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{0x00u, Opcode::DS_ADD_U32, 1, 32}, {0x01u, Opcode::DS_SUB_U32, 1, 32},
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{0x03u, Opcode::DS_INC_U32, 1, 32}, {0x04u, Opcode::DS_DEC_U32, 1, 32},
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{0x05u, Opcode::DS_MIN_I32, 1, 32}, {0x06u, Opcode::DS_MAX_I32, 1, 32},
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{0x07u, Opcode::DS_MIN_U32, 1, 32}, {0x08u, Opcode::DS_MAX_U32, 1, 32},
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{0x09u, Opcode::DS_AND_B32, 1, 32}, {0x0au, Opcode::DS_OR_B32, 1, 32},
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@@ -168,7 +169,9 @@ bool IsDsAtomicOpcode(Opcode opcode) {
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case Opcode::DS_ADD_RTN_U32:
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case Opcode::DS_SUB_U32:
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case Opcode::DS_SUB_RTN_U32:
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case Opcode::DS_INC_U32:
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case Opcode::DS_INC_RTN_U32:
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case Opcode::DS_DEC_U32:
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case Opcode::DS_DEC_RTN_U32:
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case Opcode::DS_MIN_I32:
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case Opcode::DS_MIN_RTN_I32:
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@@ -659,7 +659,9 @@ std::string InstructionToString(const Instruction& inst) {
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case Opcode::DS_ADD_RTN_U32:
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case Opcode::DS_SUB_U32:
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case Opcode::DS_SUB_RTN_U32:
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case Opcode::DS_INC_U32:
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case Opcode::DS_INC_RTN_U32:
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case Opcode::DS_DEC_U32:
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case Opcode::DS_DEC_RTN_U32:
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case Opcode::DS_MIN_I32:
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case Opcode::DS_MIN_RTN_I32:
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@@ -502,7 +502,9 @@ enum class Opcode {
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DS_ADD_RTN_U32,
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DS_SUB_U32,
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DS_SUB_RTN_U32,
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DS_INC_U32,
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DS_INC_RTN_U32,
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DS_DEC_U32,
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DS_DEC_RTN_U32,
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DS_MIN_I32,
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DS_MIN_RTN_I32,
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@@ -963,8 +963,12 @@ bool Translator::EmitMemory(const Decoder::Instruction& inst) {
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return DS_ATOMIC(inst, IR::ValueOpcode::SharedAtomicISub32, false);
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case Decoder::Opcode::DS_SUB_RTN_U32:
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return DS_ATOMIC(inst, IR::ValueOpcode::SharedAtomicISub32, true);
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case Decoder::Opcode::DS_INC_U32:
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return DS_ATOMIC(inst, IR::ValueOpcode::SharedAtomicInc32, false);
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case Decoder::Opcode::DS_INC_RTN_U32:
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return DS_ATOMIC(inst, IR::ValueOpcode::SharedAtomicInc32, true);
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case Decoder::Opcode::DS_DEC_U32:
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return DS_ATOMIC(inst, IR::ValueOpcode::SharedAtomicDec32, false);
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case Decoder::Opcode::DS_DEC_RTN_U32:
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return DS_ATOMIC(inst, IR::ValueOpcode::SharedAtomicDec32, true);
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case Decoder::Opcode::DS_MIN_I32:
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