mirror of
https://github.com/KytyPS5/KytyPS5.git
synced 2026-10-29 16:51:20 +00:00
simplify guest gpu
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e699a35f20
commit
5b730d4df0
6 files changed
+43
-267
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@@ -1934,13 +1934,7 @@ KYTY_CP_OP_PARSER(CpOpIndirectBuffer) {
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auto* indirect_buffer =
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auto* indirect_buffer =
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reinterpret_cast<const uint32_t*>(buffer[0] | (static_cast<uint64_t>(buffer[1]) << 32u));
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reinterpret_cast<const uint32_t*>(buffer[0] | (static_cast<uint64_t>(buffer[1]) << 32u));
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uint32_t indirect_num_dw = control & 0xfffffu;
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const uint32_t indirect_num_dw = control & 0xfffffu;
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static std::atomic<uint32_t> indirect_log_count {0};
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if (indirect_log_count.fetch_add(1) < 128) {
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LOGF("\t indirect buffer: addr=0x%016" PRIx64 ", num_dw=%" PRIu32 ", control=0x%08" PRIx32
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"\n",
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reinterpret_cast<uint64_t>(indirect_buffer), indirect_num_dw, control);
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}
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if (indirect_num_dw == 0) {
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if (indirect_num_dw == 0) {
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return 3;
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return 3;
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@@ -1072,8 +1072,7 @@ void CommandProcessor::WriteAtEndOfPipe(uint32_t cache_policy, uint32_t event_wr
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case 0x03: with_interrupt = false; break;
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case 0x03: with_interrupt = false; break;
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case 0x01:
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case 0x01:
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if (!IsAsyncComputeQueue()) {
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if (!IsAsyncComputeQueue()) {
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Sync::TriggerEopEventAtEndOfPipe(command, m_interrupt_event_id,
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TriggerEopEventAtEndOfPipe(interrupt_context_id);
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interrupt_context_id);
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return;
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return;
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}
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}
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with_interrupt = true;
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with_interrupt = true;
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@@ -1082,24 +1081,15 @@ void CommandProcessor::WriteAtEndOfPipe(uint32_t cache_policy, uint32_t event_wr
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default: EXIT("unknown interrupt_selector\n");
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default: EXIT("unknown interrupt_selector\n");
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}
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}
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auto write32 = [&](bool with_writeback) {
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auto write32 = [&] {
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auto* dst = static_cast<uint32_t*>(dst_gpu_addr);
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auto* dst = static_cast<uint32_t*>(dst_gpu_addr);
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auto data = static_cast<uint32_t>(value);
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auto data = static_cast<uint32_t>(value);
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EXIT_IF(dst == nullptr);
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(void)command.Handle();
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std::memcpy(dst, &data, sizeof(data));
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std::memcpy(dst, &data, sizeof(data));
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if (with_interrupt) {
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if (with_interrupt) {
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if (with_writeback) {
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TriggerEopEventAtEndOfPipe(interrupt_context_id);
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Sync::WriteAtEndOfPipeWithInterruptWriteBack32(m_submit_id, command, dst,
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data, m_interrupt_event_id,
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interrupt_context_id);
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} else {
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Sync::WriteAtEndOfPipeWithInterrupt32(m_submit_id, command, dst, data,
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m_interrupt_event_id, interrupt_context_id);
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}
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} else if (with_writeback) {
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Sync::WriteAtEndOfPipeWithWriteBack32(m_submit_id, command, dst, data);
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} else {
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Sync::WriteAtEndOfPipe32(m_submit_id, command, dst, data);
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}
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}
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};
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};
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@@ -1111,15 +1101,13 @@ void CommandProcessor::WriteAtEndOfPipe(uint32_t cache_policy, uint32_t event_wr
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SynchronizeGpu();
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SynchronizeGpu();
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Sync::ReadGds(*m_renderer.GetBufferCache().GetGdsBuffer(), dst, value & 0xffffu,
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Sync::ReadGds(*m_renderer.GetBufferCache().GetGdsBuffer(), dst, value & 0xffffu,
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value >> 16u);
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value >> 16u);
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Sync::WriteAtEndOfPipeGds32(m_submit_id, command, dst, value & 0xffffu,
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value >> 16u);
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if (with_interrupt) {
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if (with_interrupt) {
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m_renderer.TriggerInterrupt(m_interrupt_event_id, interrupt_context_id);
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m_renderer.TriggerInterrupt(m_interrupt_event_id, interrupt_context_id);
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}
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}
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return;
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return;
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}
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}
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} else if (eop_event_type == 0x04 && cache_action == 0x00 && event_index == 0x05) {
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} else if (eop_event_type == 0x04 && cache_action == 0x00 && event_index == 0x05) {
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write32(false);
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write32();
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return;
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return;
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}
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}
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break;
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break;
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@@ -1128,8 +1116,8 @@ void CommandProcessor::WriteAtEndOfPipe(uint32_t cache_policy, uint32_t event_wr
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if constexpr (sizeof(T) == sizeof(uint32_t)) {
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if constexpr (sizeof(T) == sizeof(uint32_t)) {
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if (event_write_source == 0x02 && eop_event_type == 0x2f && event_index == 0x06) {
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if (event_write_source == 0x02 && eop_event_type == 0x2f && event_index == 0x06) {
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switch (cache_action) {
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switch (cache_action) {
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case 0x00: write32(false); return;
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case 0x00:
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case 0x38: write32(true); return;
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case 0x38: write32(); return;
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default: break;
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default: break;
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}
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}
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}
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}
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@@ -1137,25 +1125,14 @@ void CommandProcessor::WriteAtEndOfPipe(uint32_t cache_policy, uint32_t event_wr
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if (event_write_source == 0x04) {
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if (event_write_source == 0x04) {
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value = Sync::ReadReferenceClock();
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value = Sync::ReadReferenceClock();
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}
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}
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auto write64 = [&](bool with_writeback) {
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auto write64 = [&] {
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auto* dst = static_cast<uint64_t*>(dst_gpu_addr);
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auto* dst = static_cast<uint64_t*>(dst_gpu_addr);
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EXIT_IF(dst == nullptr);
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(void)command.Handle();
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std::memcpy(dst, &value, sizeof(value));
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std::memcpy(dst, &value, sizeof(value));
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if (with_interrupt) {
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if (with_interrupt) {
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if (with_writeback) {
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TriggerEopEventAtEndOfPipe(interrupt_context_id);
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Sync::WriteAtEndOfPipeWithInterruptWriteBack64(
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m_submit_id, command, dst, value, m_interrupt_event_id,
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interrupt_context_id);
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} else {
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Sync::WriteAtEndOfPipeWithInterrupt64(m_submit_id, command, dst,
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value, m_interrupt_event_id,
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interrupt_context_id);
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}
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} else if (with_writeback) {
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Sync::WriteAtEndOfPipeWithWriteBack64(m_submit_id, command, dst,
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value);
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} else {
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Sync::WriteAtEndOfPipe64(m_submit_id, command, dst, value);
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}
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}
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};
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};
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@@ -1164,7 +1141,7 @@ void CommandProcessor::WriteAtEndOfPipe(uint32_t cache_policy, uint32_t event_wr
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switch (eop_event_type) {
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switch (eop_event_type) {
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case 0x04:
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case 0x04:
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if (event_index == 0x05) {
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if (event_index == 0x05) {
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write64(false);
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write64();
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return;
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return;
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}
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}
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break;
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break;
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@@ -1172,7 +1149,7 @@ void CommandProcessor::WriteAtEndOfPipe(uint32_t cache_policy, uint32_t event_wr
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case 0x28:
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case 0x28:
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case 0x2f:
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case 0x2f:
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if (event_index == 0x00) {
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if (event_index == 0x00) {
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write64(false);
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write64();
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return;
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return;
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}
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}
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break;
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break;
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@@ -1180,7 +1157,7 @@ void CommandProcessor::WriteAtEndOfPipe(uint32_t cache_policy, uint32_t event_wr
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case 0x2d:
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case 0x2d:
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case 0x30:
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case 0x30:
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if (event_index == 0x00 && !with_interrupt) {
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if (event_index == 0x00 && !with_interrupt) {
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write64(false);
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write64();
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return;
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return;
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}
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}
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break;
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break;
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@@ -1195,20 +1172,20 @@ void CommandProcessor::WriteAtEndOfPipe(uint32_t cache_policy, uint32_t event_wr
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if (((eop_event_type == 0x04 || eop_event_type == 0x28) &&
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if (((eop_event_type == 0x04 || eop_event_type == 0x28) &&
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event_index == 0x05) ||
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event_index == 0x05) ||
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(event_index == 0x00)) {
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(event_index == 0x00)) {
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write64(true);
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write64();
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return;
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return;
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}
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}
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break;
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break;
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case 0x2b:
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case 0x2b:
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case 0x2d:
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case 0x2d:
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if (event_index == 0x00 && !with_interrupt) {
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if (event_index == 0x00 && !with_interrupt) {
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write64(true);
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write64();
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return;
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return;
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}
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}
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break;
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break;
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case 0x2f:
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case 0x2f:
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if (event_index == 0x06 && !with_interrupt) {
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if (event_index == 0x06 && !with_interrupt) {
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write64(true);
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write64();
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return;
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return;
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}
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}
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break;
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break;
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@@ -1217,7 +1194,7 @@ void CommandProcessor::WriteAtEndOfPipe(uint32_t cache_policy, uint32_t event_wr
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break;
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break;
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case 0x3b:
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case 0x3b:
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if (eop_event_type == 0x04 && event_index == 0x05 && with_interrupt) {
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if (eop_event_type == 0x04 && event_index == 0x05 && with_interrupt) {
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write64(true);
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write64();
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return;
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return;
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}
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}
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break;
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break;
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@@ -1270,7 +1247,11 @@ void CommandProcessor::EmitGlobalBarrier() {
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}
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}
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void CommandProcessor::TriggerEopEventAtEndOfPipe(uint32_t interrupt_context_id) {
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void CommandProcessor::TriggerEopEventAtEndOfPipe(uint32_t interrupt_context_id) {
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Sync::TriggerEopEventAtEndOfPipe(CurrentBuffer(), m_interrupt_event_id, interrupt_context_id);
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(void)CurrentBuffer().Handle();
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GetScheduler().DeferPriorityOperation(
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[&renderer = m_renderer, event_id = m_interrupt_event_id, interrupt_context_id] {
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renderer.TriggerInterrupt(event_id, interrupt_context_id);
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});
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}
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}
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void CommandProcessor::TriggerEvent(uint32_t event_type, uint32_t event_index,
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void CommandProcessor::TriggerEvent(uint32_t event_type, uint32_t event_index,
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@@ -1360,8 +1341,9 @@ void CommandProcessor::Flip() {
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auto& command = CurrentBuffer();
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auto& command = CurrentBuffer();
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auto request = Sync::PrepareVideoOutFlip(command, m_flip.handle, m_flip.index, m_flip.flip_mode,
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auto request = Sync::PrepareVideoOutFlip(command, m_flip.handle, m_flip.index, m_flip.flip_mode,
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m_flip.flip_arg);
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m_flip.flip_arg);
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Sync::WriteAtEndOfPipeOnlyFlip(m_submit_id, command, m_flip.handle, m_flip.index,
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(void)command.Handle();
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m_flip.flip_mode, m_flip.flip_arg, request);
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GetScheduler().DeferPriorityOperation(
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[&renderer = m_renderer, request] { renderer.GetVideoOut().CompleteFlip(request); });
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GetScheduler().Flush();
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GetScheduler().Flush();
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}
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}
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@@ -1375,12 +1357,13 @@ void CommandProcessor::Flip(void* dst_gpu_addr, uint32_t value) {
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reinterpret_cast<uint64_t>(dst_gpu_addr), value);
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reinterpret_cast<uint64_t>(dst_gpu_addr), value);
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}
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}
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EXIT_IF(dst_gpu_addr == nullptr);
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std::memcpy(dst_gpu_addr, &value, sizeof(value));
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std::memcpy(dst_gpu_addr, &value, sizeof(value));
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auto request = Sync::PrepareVideoOutFlip(command, m_flip.handle, m_flip.index, m_flip.flip_mode,
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auto request = Sync::PrepareVideoOutFlip(command, m_flip.handle, m_flip.index, m_flip.flip_mode,
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m_flip.flip_arg);
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m_flip.flip_arg);
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Sync::WriteAtEndOfPipeWithFlip32(m_submit_id, command, static_cast<uint32_t*>(dst_gpu_addr),
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(void)command.Handle();
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value, m_flip.handle, m_flip.index, m_flip.flip_mode,
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GetScheduler().DeferPriorityOperation(
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m_flip.flip_arg, request);
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[&renderer = m_renderer, request] { renderer.GetVideoOut().CompleteFlip(request); });
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GetScheduler().Flush();
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GetScheduler().Flush();
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}
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}
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@@ -1400,12 +1383,16 @@ void CommandProcessor::FlipWithInterrupt(uint32_t eop_event_type, uint32_t cache
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if (eop_event_type != 0x00000004 || cache_action != 0x00000038) {
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if (eop_event_type != 0x00000004 || cache_action != 0x00000038) {
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EXIT("unknown event type\n");
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EXIT("unknown event type\n");
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}
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}
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EXIT_IF(dst_gpu_addr == nullptr);
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std::memcpy(dst_gpu_addr, &value, sizeof(value));
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std::memcpy(dst_gpu_addr, &value, sizeof(value));
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auto request = Sync::PrepareVideoOutFlip(command, m_flip.handle, m_flip.index, m_flip.flip_mode,
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auto request = Sync::PrepareVideoOutFlip(command, m_flip.handle, m_flip.index, m_flip.flip_mode,
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m_flip.flip_arg);
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m_flip.flip_arg);
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Sync::WriteAtEndOfPipeWithInterruptWriteBackFlip32(
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(void)command.Handle();
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m_submit_id, command, static_cast<uint32_t*>(dst_gpu_addr), value, m_flip.handle,
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GetScheduler().DeferPriorityOperation(
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m_flip.index, m_flip.flip_mode, m_flip.flip_arg, request, m_interrupt_event_id);
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[&renderer = m_renderer, event_id = m_interrupt_event_id, request] {
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renderer.GetVideoOut().CompleteFlip(request);
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renderer.TriggerInterrupt(event_id, 0);
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});
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GetScheduler().Flush();
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GetScheduler().Flush();
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}
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}
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@@ -1932,6 +1932,9 @@ void TextureCache::RunGarbageCollector() {
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}
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}
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void TextureCache::ProcessDownloadImages() {
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void TextureCache::ProcessDownloadImages() {
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if (!m_readback_linear_images) {
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return;
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}
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std::scoped_lock lock {m_lock};
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std::scoped_lock lock {m_lock};
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for (const auto id: m_download_images) {
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for (const auto id: m_download_images) {
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const auto owner = m_slot_images.try_get(id);
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const auto owner = m_slot_images.try_get(id);
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@@ -39,13 +39,7 @@ enum class CommandBufferDebugOp : uint32_t {
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DispatchDirect,
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DispatchDirect,
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DrawIndex,
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DrawIndex,
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DrawIndexAuto,
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DrawIndexAuto,
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EopWrite,
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DispatchIndirect = 9,
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EopInterrupt,
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EopWriteBack,
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EopFlip,
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EopWriteBackFlip,
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EopOnlyFlip,
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DispatchIndirect,
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Unknown,
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Unknown,
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};
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};
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@@ -1,10 +1,6 @@
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#include "graphics/host_gpu/renderer/sync.h"
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#include "graphics/host_gpu/renderer/sync.h"
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#include "common/assert.h"
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#include "common/assert.h"
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#include "common/common.h"
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#include "common/logging/log.h"
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#include "common/threads.h"
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#include "graphics/host_gpu/graphicContext.h"
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#include "graphics/host_gpu/renderer/cache/bufferCache.h"
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#include "graphics/host_gpu/renderer/cache/bufferCache.h"
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#include "graphics/host_gpu/renderer/render.h"
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#include "graphics/host_gpu/renderer/render.h"
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#include "graphics/host_gpu/renderer/renderContext.h"
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#include "graphics/host_gpu/renderer/renderContext.h"
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@@ -53,109 +49,6 @@ uint64_t ReadReferenceClock() {
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return value;
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return value;
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}
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}
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enum class EndOfPipeWriteSize : uint32_t { Dword = 4, Qword = 8 };
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enum class EndOfPipeWriteAction { Write, WriteBack, Interrupt, InterruptWriteBack };
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static CommandBufferDebugOp DebugOperation(EndOfPipeWriteAction action) {
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switch (action) {
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case EndOfPipeWriteAction::Write: return CommandBufferDebugOp::EopWrite;
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case EndOfPipeWriteAction::WriteBack:
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case EndOfPipeWriteAction::InterruptWriteBack: return CommandBufferDebugOp::EopWriteBack;
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case EndOfPipeWriteAction::Interrupt: return CommandBufferDebugOp::EopInterrupt;
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}
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EXIT("unsupported end-of-pipe write action\n");
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return CommandBufferDebugOp::Unknown;
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}
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static bool TriggersInterrupt(EndOfPipeWriteAction action) {
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return action == EndOfPipeWriteAction::Interrupt ||
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action == EndOfPipeWriteAction::InterruptWriteBack;
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}
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static void RecordEndOfPipeWrite(uint64_t submit_id, CommandBuffer& buffer, uint64_t destination,
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uint64_t value, EndOfPipeWriteSize size,
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EndOfPipeWriteAction action, int interrupt_event_id = 0,
|
|
||||||
uint32_t context_id = 0) {
|
|
||||||
EXIT_IF(destination == 0);
|
|
||||||
(void)buffer.Handle();
|
|
||||||
|
|
||||||
const auto width = static_cast<uint32_t>(size);
|
|
||||||
const auto value_low = static_cast<uint32_t>(value);
|
|
||||||
const auto value_high = static_cast<uint32_t>(value >> 32u);
|
|
||||||
const auto operation = static_cast<uint32_t>(DebugOperation(action));
|
|
||||||
if (TriggersInterrupt(action)) {
|
|
||||||
buffer.SetDebugInfo(operation, submit_id, width, context_id, value_low, value_high,
|
|
||||||
destination);
|
|
||||||
TriggerEopEventAtEndOfPipe(buffer, interrupt_event_id, context_id);
|
|
||||||
} else {
|
|
||||||
buffer.SetDebugInfo(operation, submit_id, width, value_low, value_high, 0, destination);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
void WriteAtEndOfPipe32(uint64_t submit_id, CommandBuffer& buffer, uint32_t* dst_gpu_addr,
|
|
||||||
uint32_t value) {
|
|
||||||
RecordEndOfPipeWrite(submit_id, buffer, reinterpret_cast<uint64_t>(dst_gpu_addr), value,
|
|
||||||
EndOfPipeWriteSize::Dword, EndOfPipeWriteAction::Write);
|
|
||||||
}
|
|
||||||
|
|
||||||
void WriteAtEndOfPipeGds32(uint64_t submit_id, CommandBuffer& buffer, uint32_t* dst_gpu_addr,
|
|
||||||
uint32_t dw_offset, uint32_t dw_num) {
|
|
||||||
EXIT_IF(dst_gpu_addr == nullptr);
|
|
||||||
(void)buffer.Handle();
|
|
||||||
buffer.SetDebugInfo(static_cast<uint32_t>(CommandBufferDebugOp::EopWrite), submit_id,
|
|
||||||
dw_offset, dw_num, 0, 0, reinterpret_cast<uint64_t>(dst_gpu_addr));
|
|
||||||
}
|
|
||||||
|
|
||||||
void WriteAtEndOfPipe64(uint64_t submit_id, CommandBuffer& buffer, uint64_t* dst_gpu_addr,
|
|
||||||
uint64_t value) {
|
|
||||||
RecordEndOfPipeWrite(submit_id, buffer, reinterpret_cast<uint64_t>(dst_gpu_addr), value,
|
|
||||||
EndOfPipeWriteSize::Qword, EndOfPipeWriteAction::Write);
|
|
||||||
}
|
|
||||||
|
|
||||||
void WriteAtEndOfPipeWithWriteBack64(uint64_t submit_id, CommandBuffer& buffer,
|
|
||||||
uint64_t* dst_gpu_addr, uint64_t value) {
|
|
||||||
RecordEndOfPipeWrite(submit_id, buffer, reinterpret_cast<uint64_t>(dst_gpu_addr), value,
|
|
||||||
EndOfPipeWriteSize::Qword, EndOfPipeWriteAction::WriteBack);
|
|
||||||
}
|
|
||||||
|
|
||||||
void WriteAtEndOfPipeWithWriteBack32(uint64_t submit_id, CommandBuffer& buffer,
|
|
||||||
uint32_t* dst_gpu_addr, uint32_t value) {
|
|
||||||
RecordEndOfPipeWrite(submit_id, buffer, reinterpret_cast<uint64_t>(dst_gpu_addr), value,
|
|
||||||
EndOfPipeWriteSize::Dword, EndOfPipeWriteAction::WriteBack);
|
|
||||||
}
|
|
||||||
|
|
||||||
void WriteAtEndOfPipeWithInterruptWriteBack64(uint64_t submit_id, CommandBuffer& buffer,
|
|
||||||
uint64_t* dst_gpu_addr, uint64_t value, int event_id,
|
|
||||||
uint32_t context_id) {
|
|
||||||
RecordEndOfPipeWrite(submit_id, buffer, reinterpret_cast<uint64_t>(dst_gpu_addr), value,
|
|
||||||
EndOfPipeWriteSize::Qword, EndOfPipeWriteAction::InterruptWriteBack,
|
|
||||||
event_id, context_id);
|
|
||||||
}
|
|
||||||
|
|
||||||
void WriteAtEndOfPipeWithInterruptWriteBack32(uint64_t submit_id, CommandBuffer& buffer,
|
|
||||||
uint32_t* dst_gpu_addr, uint32_t value, int event_id,
|
|
||||||
uint32_t context_id) {
|
|
||||||
RecordEndOfPipeWrite(submit_id, buffer, reinterpret_cast<uint64_t>(dst_gpu_addr), value,
|
|
||||||
EndOfPipeWriteSize::Dword, EndOfPipeWriteAction::InterruptWriteBack,
|
|
||||||
event_id, context_id);
|
|
||||||
}
|
|
||||||
|
|
||||||
void WriteAtEndOfPipeWithInterrupt64(uint64_t submit_id, CommandBuffer& buffer,
|
|
||||||
uint64_t* dst_gpu_addr, uint64_t value, int event_id,
|
|
||||||
uint32_t context_id) {
|
|
||||||
RecordEndOfPipeWrite(submit_id, buffer, reinterpret_cast<uint64_t>(dst_gpu_addr), value,
|
|
||||||
EndOfPipeWriteSize::Qword, EndOfPipeWriteAction::Interrupt, event_id,
|
|
||||||
context_id);
|
|
||||||
}
|
|
||||||
|
|
||||||
void WriteAtEndOfPipeWithInterrupt32(uint64_t submit_id, CommandBuffer& buffer,
|
|
||||||
uint32_t* dst_gpu_addr, uint32_t value, int event_id,
|
|
||||||
uint32_t context_id) {
|
|
||||||
RecordEndOfPipeWrite(submit_id, buffer, reinterpret_cast<uint64_t>(dst_gpu_addr), value,
|
|
||||||
EndOfPipeWriteSize::Dword, EndOfPipeWriteAction::Interrupt, event_id,
|
|
||||||
context_id);
|
|
||||||
}
|
|
||||||
|
|
||||||
uint64_t PrepareVideoOutFlip(CommandBuffer& buffer, int handle, int index, int flip_mode,
|
uint64_t PrepareVideoOutFlip(CommandBuffer& buffer, int handle, int index, int flip_mode,
|
||||||
int64_t flip_arg) {
|
int64_t flip_arg) {
|
||||||
for (;;) {
|
for (;;) {
|
||||||
@@ -176,65 +69,6 @@ uint64_t PrepareVideoOutFlip(CommandBuffer& buffer, int handle, int index, int f
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
void WriteAtEndOfPipeWithInterruptWriteBackFlip32(uint64_t submit_id, CommandBuffer& buffer,
|
|
||||||
uint32_t* dst_gpu_addr, uint32_t value,
|
|
||||||
int handle, int index, int flip_mode,
|
|
||||||
int64_t flip_arg, uint64_t request_id,
|
|
||||||
int event_id) {
|
|
||||||
EXIT_IF(dst_gpu_addr == nullptr);
|
|
||||||
(void)buffer.Handle();
|
|
||||||
buffer.SetDebugInfo(static_cast<uint32_t>(CommandBufferDebugOp::EopWriteBackFlip), submit_id,
|
|
||||||
static_cast<uint32_t>(handle), static_cast<uint32_t>(index),
|
|
||||||
static_cast<uint32_t>(flip_mode), value, static_cast<uint64_t>(flip_arg));
|
|
||||||
|
|
||||||
auto& renderer = buffer.GetContext();
|
|
||||||
auto& scheduler = renderer.GetCommandScheduler();
|
|
||||||
EXIT_IF(!scheduler.Active() || &buffer != &scheduler.Current());
|
|
||||||
scheduler.DeferPriorityOperation([&renderer, event_id, request_id] {
|
|
||||||
renderer.GetVideoOut().CompleteFlip(request_id);
|
|
||||||
renderer.TriggerInterrupt(event_id, 0);
|
|
||||||
});
|
|
||||||
}
|
|
||||||
|
|
||||||
void WriteAtEndOfPipeWithFlip32(uint64_t submit_id, CommandBuffer& buffer, uint32_t* dst_gpu_addr,
|
|
||||||
uint32_t value, int handle, int index, int flip_mode,
|
|
||||||
int64_t flip_arg, uint64_t request_id) {
|
|
||||||
EXIT_IF(dst_gpu_addr == nullptr);
|
|
||||||
(void)buffer.Handle();
|
|
||||||
buffer.SetDebugInfo(static_cast<uint32_t>(CommandBufferDebugOp::EopFlip), submit_id,
|
|
||||||
static_cast<uint32_t>(handle), static_cast<uint32_t>(index),
|
|
||||||
static_cast<uint32_t>(flip_mode), value, static_cast<uint64_t>(flip_arg));
|
|
||||||
|
|
||||||
auto& renderer = buffer.GetContext();
|
|
||||||
auto& scheduler = renderer.GetCommandScheduler();
|
|
||||||
EXIT_IF(!scheduler.Active() || &buffer != &scheduler.Current());
|
|
||||||
scheduler.DeferPriorityOperation(
|
|
||||||
[&renderer, request_id] { renderer.GetVideoOut().CompleteFlip(request_id); });
|
|
||||||
}
|
|
||||||
|
|
||||||
void WriteAtEndOfPipeOnlyFlip(uint64_t submit_id, CommandBuffer& buffer, int handle, int index,
|
|
||||||
int flip_mode, int64_t flip_arg, uint64_t request_id) {
|
|
||||||
(void)buffer.Handle();
|
|
||||||
buffer.SetDebugInfo(static_cast<uint32_t>(CommandBufferDebugOp::EopOnlyFlip), submit_id,
|
|
||||||
static_cast<uint32_t>(handle), static_cast<uint32_t>(index),
|
|
||||||
static_cast<uint32_t>(flip_mode), 0, static_cast<uint64_t>(flip_arg));
|
|
||||||
|
|
||||||
auto& renderer = buffer.GetContext();
|
|
||||||
auto& scheduler = renderer.GetCommandScheduler();
|
|
||||||
EXIT_IF(!scheduler.Active() || &buffer != &scheduler.Current());
|
|
||||||
scheduler.DeferPriorityOperation(
|
|
||||||
[&renderer, request_id] { renderer.GetVideoOut().CompleteFlip(request_id); });
|
|
||||||
}
|
|
||||||
|
|
||||||
void TriggerEopEventAtEndOfPipe(CommandBuffer& buffer, int event_id, uint32_t context_id) {
|
|
||||||
(void)buffer.Handle();
|
|
||||||
auto& renderer = buffer.GetContext();
|
|
||||||
auto& scheduler = renderer.GetCommandScheduler();
|
|
||||||
EXIT_IF(!scheduler.Active() || &buffer != &scheduler.Current());
|
|
||||||
scheduler.DeferPriorityOperation(
|
|
||||||
[&renderer, event_id, context_id] { renderer.TriggerInterrupt(event_id, context_id); });
|
|
||||||
}
|
|
||||||
|
|
||||||
static void InterruptEventResetFunc(LibKernel::EventQueue::KernelEqueueEvent* event) {
|
static void InterruptEventResetFunc(LibKernel::EventQueue::KernelEqueueEvent* event) {
|
||||||
EXIT_IF(event == nullptr);
|
EXIT_IF(event == nullptr);
|
||||||
event->triggered = false;
|
event->triggered = false;
|
||||||
|
|||||||
@@ -17,44 +17,8 @@ namespace Sync {
|
|||||||
uint64_t& value);
|
uint64_t& value);
|
||||||
[[nodiscard]] uint64_t ReadReferenceClock();
|
[[nodiscard]] uint64_t ReadReferenceClock();
|
||||||
|
|
||||||
void TriggerEopEventAtEndOfPipe(CommandBuffer& buffer, int event_id, uint32_t context_id);
|
|
||||||
|
|
||||||
void WriteAtEndOfPipe32(uint64_t submit_id, CommandBuffer& buffer, uint32_t* dst_gpu_addr,
|
|
||||||
uint32_t value);
|
|
||||||
void WriteAtEndOfPipe64(uint64_t submit_id, CommandBuffer& buffer, uint64_t* dst_gpu_addr,
|
|
||||||
uint64_t value);
|
|
||||||
void WriteAtEndOfPipeGds32(uint64_t submit_id, CommandBuffer& buffer, uint32_t* dst_gpu_addr,
|
|
||||||
uint32_t dw_offset, uint32_t dw_num);
|
|
||||||
void WriteAtEndOfPipeWithWriteBack32(uint64_t submit_id, CommandBuffer& buffer,
|
|
||||||
uint32_t* dst_gpu_addr, uint32_t value);
|
|
||||||
void WriteAtEndOfPipeWithWriteBack64(uint64_t submit_id, CommandBuffer& buffer,
|
|
||||||
uint64_t* dst_gpu_addr, uint64_t value);
|
|
||||||
void WriteAtEndOfPipeWithInterrupt32(uint64_t submit_id, CommandBuffer& buffer,
|
|
||||||
uint32_t* dst_gpu_addr, uint32_t value, int event_id,
|
|
||||||
uint32_t context_id = 0);
|
|
||||||
void WriteAtEndOfPipeWithInterrupt64(uint64_t submit_id, CommandBuffer& buffer,
|
|
||||||
uint64_t* dst_gpu_addr, uint64_t value, int event_id,
|
|
||||||
uint32_t context_id = 0);
|
|
||||||
void WriteAtEndOfPipeWithInterruptWriteBack32(uint64_t submit_id, CommandBuffer& buffer,
|
|
||||||
uint32_t* dst_gpu_addr, uint32_t value, int event_id,
|
|
||||||
uint32_t context_id = 0);
|
|
||||||
void WriteAtEndOfPipeWithInterruptWriteBack64(uint64_t submit_id, CommandBuffer& buffer,
|
|
||||||
uint64_t* dst_gpu_addr, uint64_t value, int event_id,
|
|
||||||
uint32_t context_id = 0);
|
|
||||||
|
|
||||||
[[nodiscard]] uint64_t PrepareVideoOutFlip(CommandBuffer& buffer, int handle, int index,
|
[[nodiscard]] uint64_t PrepareVideoOutFlip(CommandBuffer& buffer, int handle, int index,
|
||||||
int flip_mode, int64_t flip_arg);
|
int flip_mode, int64_t flip_arg);
|
||||||
void WriteAtEndOfPipeOnlyFlip(uint64_t submit_id, CommandBuffer& buffer, int handle, int index,
|
|
||||||
int flip_mode, int64_t flip_arg, uint64_t request_id);
|
|
||||||
void WriteAtEndOfPipeWithFlip32(uint64_t submit_id, CommandBuffer& buffer, uint32_t* dst_gpu_addr,
|
|
||||||
uint32_t value, int handle, int index, int flip_mode,
|
|
||||||
int64_t flip_arg, uint64_t request_id);
|
|
||||||
void WriteAtEndOfPipeWithInterruptWriteBackFlip32(uint64_t submit_id, CommandBuffer& buffer,
|
|
||||||
uint32_t* dst_gpu_addr, uint32_t value,
|
|
||||||
int handle, int index, int flip_mode,
|
|
||||||
int64_t flip_arg, uint64_t request_id,
|
|
||||||
int event_id);
|
|
||||||
|
|
||||||
int AddEqEvent(RenderContext& renderer, LibKernel::EventQueue::KernelEqueue eq, int id,
|
int AddEqEvent(RenderContext& renderer, LibKernel::EventQueue::KernelEqueue eq, int id,
|
||||||
void* udata);
|
void* udata);
|
||||||
int DeleteEqEvent(RenderContext& renderer, LibKernel::EventQueue::KernelEqueue eq, int id);
|
int DeleteEqEvent(RenderContext& renderer, LibKernel::EventQueue::KernelEqueue eq, int id);
|
||||||
|
|||||||
Reference in new issue
Block a user