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shader: load the DPP lane id once for both partial write masks

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nmzik committed 2026-10-22 01:01:38 +02:00
1 parent 11465a5e3c
commit 64186404a3
1 file changed
+3 -2
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src/graphics/shader/recompiler/backend/spirv/spirvEmitterFlow.cpp
+3 -2
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@@ -116,12 +116,13 @@ uint32_t EmitDppWriteCondition(ValueEmitContext& ctx, const IR::DppMoveFlags& fl
uint32_t exec) { uint32_t exec) {
auto& state = ctx.state; auto& state = ctx.state;
uint32_t writable = exec; uint32_t writable = exec;
uint32_t lane = 0;
// Each mask bit enables writes to one bank (4 lanes) or row (16 lanes); a full mask enables all. // Each mask bit enables writes to one bank (4 lanes) or row (16 lanes); a full mask enables all.
const auto enable = [&](uint32_t mask, uint32_t group_shift) { const auto enable = [&](uint32_t mask, uint32_t group_shift) {
if (mask == 0xfu) return; if (mask == 0xfu) return;
lane = lane != 0 ? lane : EmitSubgroupLocalInvocationId(state);
const auto group = EmitNative<spv::OpBitFieldUExtract, IR::Type::U32>( const auto group = EmitNative<spv::OpBitFieldUExtract, IR::Type::U32>(
state, EmitSubgroupLocalInvocationId(state), ConstantU32(state, group_shift), state, lane, ConstantU32(state, group_shift), ConstantU32(state, 2));
ConstantU32(state, 2));
const auto bit = EmitNative<spv::OpBitFieldUExtract, IR::Type::U32>( const auto bit = EmitNative<spv::OpBitFieldUExtract, IR::Type::U32>(
state, ConstantU32(state, mask), group, ConstantU32(state, 1)); state, ConstantU32(state, mask), group, ConstantU32(state, 1));
writable = Binary(state, spv::OpLogicalAnd, TypeBool(state), writable, writable = Binary(state, spv::OpLogicalAnd, TypeBool(state), writable,