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shader: decode s_dcache_inv as a no-op
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@@ -22,7 +22,7 @@ constexpr MemoryOpcodeInfo SMEM_OPCODE_LIST[] = {
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{0x04u, Opcode::S_LOAD_DWORDX16, 16, 32}, {0x08u, Opcode::S_BUFFER_LOAD_DWORD, 1, 32},
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{0x09u, Opcode::S_BUFFER_LOAD_DWORDX2, 2, 32}, {0x0au, Opcode::S_BUFFER_LOAD_DWORDX4, 4, 32},
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{0x0bu, Opcode::S_BUFFER_LOAD_DWORDX8, 8, 32}, {0x0cu, Opcode::S_BUFFER_LOAD_DWORDX16, 16, 32},
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{0x25u, Opcode::S_MEMREALTIME, 2, 32},
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{0x20u, Opcode::S_DCACHE_INV, 0, 0}, {0x25u, Opcode::S_MEMREALTIME, 2, 32},
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};
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constexpr MemoryOpcodeInfo MUBUF_OPCODE_LIST[] = {
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@@ -286,6 +286,9 @@ void DecodeSmem(uint32_t pc, std::span<const uint32_t> code, uint32_t word_index
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if (inst.opcode == Opcode::UNSUPPORTED) {
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SetUnsupported(inst, Family::SMEM, opcode, "SMEM opcode is not implemented");
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}
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if (inst.opcode == Opcode::S_DCACHE_INV) {
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return;
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}
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DecodeScalarDestination(sdst, pc, inst.dst);
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if (inst.opcode == Opcode::S_MEMREALTIME) {
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@@ -557,6 +557,7 @@ std::string InstructionToString(const Instruction& inst) {
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OperandToString(inst.src0).c_str()));
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case Opcode::S_BARRIER:
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return WithUnsupportedReason(inst, fmt::format("0x{:08x}: s_barrier", inst.pc));
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case Opcode::S_DCACHE_INV:
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case Opcode::BUFFER_GL0_INV:
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case Opcode::BUFFER_GL1_INV:
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return fmt::format("0x{:08x}: {}", inst.pc, magic_enum::enum_name(inst.opcode));
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@@ -544,6 +544,7 @@ enum class Opcode {
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S_BUFFER_LOAD_DWORDX8,
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S_BUFFER_LOAD_DWORDX16,
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S_MEMREALTIME,
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S_DCACHE_INV,
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BUFFER_LOAD_FORMAT_X,
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BUFFER_LOAD_FORMAT_XY,
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BUFFER_LOAD_FORMAT_XYZ,
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@@ -941,6 +941,8 @@ void Translator::DS_PERMUTE(const Decoder::Instruction& inst, bool backward) {
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void Translator::EmitMemory(const Decoder::Instruction& inst) {
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switch (inst.opcode) {
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// Translated scalar loads have no cache of their own to invalidate.
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case Decoder::Opcode::S_DCACHE_INV: return;
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case Decoder::Opcode::BUFFER_GL0_INV:
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case Decoder::Opcode::BUFFER_GL1_INV:
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ir.Emit(IR::ValueOpcode::DataCacheInvalidate);
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@@ -2001,18 +2001,21 @@ void TestNggVertexEntryState() {
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void TestNativeDataCacheInvalidation() {
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using namespace ShaderRecompiler;
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// Captured f5edf70dbb1f6057:0x194 and 0x1a4, each followed by S_WAITCNT.
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// Captured f5edf70dbb1f6057:0x194 and 0x1a4, each followed by S_WAITCNT. The S_DCACHE_INV
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// after them emits no fence.
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const std::array cache_ops = {0xe1c40000u, 0u, 0xbf8c0000u,
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0xe1c80000u, 0u, 0xbf8c0000u, EncodeSopp(0x01)};
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0xe1c80000u, 0u, 0xbf8c0000u,
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0xf4800000u, 0xfa000000u, EncodeSopp(0x01)};
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Decoder::Program decoded;
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Decoder::DecodeProgram(cache_ops, decoded);
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for (const uint32_t index : {0u, 2u}) {
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for (const auto [index, opcode] : {std::pair{0u, Decoder::Opcode::BUFFER_GL0_INV},
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std::pair{2u, Decoder::Opcode::BUFFER_GL1_INV},
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std::pair{4u, Decoder::Opcode::S_DCACHE_INV}}) {
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const auto &inst = decoded.instructions[index];
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Check(inst.opcode == (index == 0 ? Decoder::Opcode::BUFFER_GL0_INV
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: Decoder::Opcode::BUFFER_GL1_INV) &&
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Check(inst.opcode == opcode &&
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inst.word_count == 2 && inst.src_count == 0 && inst.data_dwords == 0 &&
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inst.dst.kind == Decoder::OperandKind::Unknown,
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"RDNA2 cache invalidation acquired a buffer operand or lost its encoding");
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"RDNA2 cache invalidation acquired an operand or lost its encoding");
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}
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auto options = MakeCompileOptions(ShaderType::Compute);
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