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shader: keep fragment layer values under lane masks

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Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com>
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nmzikandshadowbeat070 committed 2026-09-05 11:43:49 +04:00
1 parent 2ec0e9e8f3
commit b96a30ed88
16 files changed
+458 -25
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src/graphics/shader/recompiler/frontend/translate/Control.cpp
+10 -3
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@@ -259,13 +259,20 @@ void Translator::S_MOV_B64(const Decoder::Instruction& inst) {
}
void Translator::S_WQM_B64(const Decoder::Instruction& inst) {
const auto mask_valid = ReadMaskValid(inst.src0);
const auto source_mask = ReadMask(inst.src0);
const auto mask_valid = ReadMaskValid(inst.src0);
const auto result =
IR::U64(ir.Emit(IR::ValueOpcode::WqmU64, {ReadOperand(inst.src0, IR::Type::U64)}));
// WQM activates whole quads and cannot clear an already active lane.
const auto widened_mask = ir.LogicalOr(source_mask, ThreadBit(ExtractU64(result)));
WriteOperand(DestinationOperand(inst), result);
if (inst.dst.kind == Decoder::OperandKind::Sgpr) {
if (inst.dst.kind == Decoder::OperandKind::ExecLo) {
ir.SetExec(widened_mask);
} else if (inst.dst.kind == Decoder::OperandKind::VccLo) {
ir.SetVcc(widened_mask);
} else if (inst.dst.kind == Decoder::OperandKind::Sgpr) {
const auto dst = static_cast<IR::ScalarReg>(inst.dst.reg);
ir.SetThreadBitScalarReg(dst, ThreadBit(ExtractU64(result)));
ir.SetThreadBitScalarReg(dst, widened_mask);
ir.SetScalarMaskTag(dst, mask_valid);
}
ir.SetScc(IR::U1(ir.Emit(IR::ValueOpcode::INotEqual64, {result, IR::Value(uint64_t {0})})));