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https://github.com/KytyPS5/KytyPS5.git
synced 2026-10-27 16:02:37 +00:00
gpu: decode RELEASE_MEM directly from the driver's native packet
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nmzik committed
1 parent
227f12ee4b
commit
bf5dd62eea
10 files changed
+121
-356
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@@ -631,18 +631,6 @@ void CommandProcessor::ProcessPm4(Pm4Execution& execution) {
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opcode, KYTY_PM4_R(packet_header), packet_dw,
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reinterpret_cast<uint64_t>(packet), packet_header);
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}
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if (opcode == Pm4::IT_NOP && KYTY_PM4_R(packet_header) == Pm4::R_RELEASE_MEM &&
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packet_dw >= 7) {
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static std::atomic<uint32_t> log_count {0};
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if (log_count.fetch_add(1) < 128) {
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const auto dst = packet[3] | (static_cast<uint64_t>(packet[4]) << 32u);
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const auto val = packet[5] | (static_cast<uint64_t>(packet[6]) << 32u);
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LOGF("\t predicated skip: R_RELEASE_MEM dst=0x%016" PRIx64
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", value=0x%016" PRIx64 ", action=0x%08" PRIx32
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", gcr/data/int=0x%08" PRIx32 "\n",
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dst, val, packet[1], packet[2]);
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}
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}
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cursor.offset_dw += packet_dw;
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execution.m_made_progress = true;
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continue;
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@@ -948,192 +936,65 @@ void CommandProcessor::WaitFlipDone(uint32_t video_out_handle, uint32_t display_
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}
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}
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template <typename T>
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void CommandProcessor::WriteAtEndOfPipe(uint32_t eop_event_type, uint32_t cache_action,
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uint32_t event_index, uint32_t event_write_source,
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void* dst_gpu_addr, T value, uint32_t interrupt_selector,
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uint32_t interrupt_context_id) {
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static_assert(sizeof(T) == sizeof(uint32_t) || sizeof(T) == sizeof(uint64_t));
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auto& command = CurrentBuffer();
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void CommandProcessor::ReleaseMem(uint32_t data_sel, uint32_t interrupt_selector, void* address,
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uint64_t data, uint32_t interrupt_context_id) {
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if (GraphicsRunDebugDumpEnabled()) {
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const auto bits = static_cast<unsigned>(sizeof(T) * 8u);
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const auto log_width = static_cast<int>(sizeof(T) * 2u);
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LOGF("CommandProcessor::ReleaseMem()\n"
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"\t data_sel = %" PRIu32 "\n"
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"\t interrupt_selector = %" PRIu32 "\n"
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"\t address = 0x%016" PRIx64 "\n"
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"\t data = 0x%016" PRIx64 "\n"
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"\t interrupt_context = 0x%08" PRIx32 "\n",
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data_sel, interrupt_selector, reinterpret_cast<uint64_t>(address), data,
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interrupt_context_id);
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}
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LOGF("CommandProcessor::WriteAtEndOfPipe%u()\n"
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"\t eop_event_type = 0x%08" PRIx32 "\n"
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"\t cache_action = 0x%08" PRIx32 "\n"
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"\t event_index = 0x%08" PRIx32 "\n"
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"\t event_write_source = 0x%08" PRIx32 "\n"
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"\t interrupt_selector = 0x%08" PRIx32 "\n"
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"\t interrupt_context = 0x%08" PRIx32 "\n"
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"\t dst_gpu_addr = 0x%016" PRIx64 "\n"
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"\t value = 0x%0*" PRIx64 "\n",
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bits, eop_event_type, cache_action, event_index, event_write_source,
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interrupt_selector, interrupt_context_id, reinterpret_cast<uint64_t>(dst_gpu_addr),
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log_width, static_cast<uint64_t>(value));
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// QueuedInterrupt: kNone, kOnly, kAfterWriteConfirm, kDataAfterWriteConfirm, kSendIntCtx.
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EXIT_NOT_IMPLEMENTED(interrupt_selector > 4);
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const bool interrupt = (interrupt_selector != 0 && interrupt_selector != 3);
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// kSendIntCtx has no label, and kOnly writes none on graphics queues.
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if (address == nullptr || interrupt_selector == 4 ||
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(interrupt_selector == 1 && !IsAsyncComputeQueue())) {
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data_sel = 0;
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}
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if (data_sel == 0 && !interrupt) {
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return;
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}
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// Dumped occlusion counters are written before any end-of-pipe signal reaches the guest.
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m_renderer.GetOcclusionQueries().Publish();
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bool with_interrupt = false;
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switch (interrupt_selector) {
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case 0x00:
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case 0x03: with_interrupt = false; break;
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case 0x01:
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if (!IsAsyncComputeQueue()) {
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TriggerEopEventAtEndOfPipe(interrupt_context_id);
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return;
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}
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with_interrupt = true;
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// EndOfPipeData: kNone, kImmediate32b, kImmediate64b, kRefClk; 5 reads GDS.
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switch (data_sel) {
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case 0: break;
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case 1: {
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const auto value = static_cast<uint32_t>(data);
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std::memcpy(address, &value, sizeof(value));
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break;
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case 0x02: with_interrupt = true; break;
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default: EXIT("unknown interrupt_selector\n");
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}
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auto write32 = [&] {
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auto* dst = static_cast<uint32_t*>(dst_gpu_addr);
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auto data = static_cast<uint32_t>(value);
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EXIT_IF(dst == nullptr);
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(void)command.Handle();
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std::memcpy(dst, &data, sizeof(data));
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if (with_interrupt) {
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TriggerEopEventAtEndOfPipe(interrupt_context_id);
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}
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};
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switch (event_write_source) {
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case 0x01:
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if constexpr (sizeof(T) == sizeof(uint32_t)) {
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if (eop_event_type == 0x2f && cache_action == 0x00 && event_index == 0x06) {
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auto* dst = static_cast<uint32_t*>(dst_gpu_addr);
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SynchronizeGpu();
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Sync::ReadGds(*m_renderer.GetBufferCache().GetGdsBuffer(), dst, value & 0xffffu,
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value >> 16u);
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if (with_interrupt) {
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m_renderer.TriggerInterrupt(m_interrupt_event_id, interrupt_context_id);
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}
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return;
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}
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case 3: data = Sync::ReadReferenceClock(); [[fallthrough]];
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case 2: std::memcpy(address, &data, sizeof(data)); break;
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case 5: {
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GetScheduler().Finish();
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const auto gds = static_cast<uint32_t>(data);
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Sync::ReadGds(*m_renderer.GetBufferCache().GetGdsBuffer(),
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static_cast<uint32_t*>(address), gds & 0xffffu, gds >> 16u);
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if (interrupt) {
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// The GPU is idle, so the interrupt needs no fence.
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m_renderer.TriggerInterrupt(m_interrupt_event_id, interrupt_context_id);
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}
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break;
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case 0x02:
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case 0x04:
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if constexpr (sizeof(T) == sizeof(uint32_t)) {
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if (event_write_source == 0x02 && eop_event_type == 0x2f && event_index == 0x06) {
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switch (cache_action) {
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case 0x00:
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case 0x38: write32(); return;
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default: break;
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}
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}
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} else {
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if (event_write_source == 0x04) {
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value = Sync::ReadReferenceClock();
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}
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auto write64 = [&] {
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auto* dst = static_cast<uint64_t*>(dst_gpu_addr);
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EXIT_IF(dst == nullptr);
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(void)command.Handle();
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std::memcpy(dst, &value, sizeof(value));
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if (with_interrupt) {
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TriggerEopEventAtEndOfPipe(interrupt_context_id);
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}
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};
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switch (cache_action) {
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case 0x00:
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switch (eop_event_type) {
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case 0x04:
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if (event_index == 0x05) {
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write64();
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return;
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}
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break;
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case 0x14:
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case 0x28:
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case 0x2f:
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if (event_index == 0x00) {
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write64();
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return;
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}
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break;
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case 0x2b:
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case 0x2d:
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case 0x30:
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if (event_index == 0x00 && !with_interrupt) {
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write64();
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return;
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}
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break;
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default: break;
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}
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break;
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case 0x38:
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switch (eop_event_type) {
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case 0x04:
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case 0x14:
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case 0x28:
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if (event_index == 0x00) {
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write64();
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return;
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}
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break;
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case 0x2b:
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case 0x2d:
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if (event_index == 0x00 && !with_interrupt) {
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write64();
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return;
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}
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break;
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case 0x2f:
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if (event_index == 0x06 && !with_interrupt) {
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write64();
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return;
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}
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break;
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default: break;
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}
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break;
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default: break;
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}
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}
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break;
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default: break;
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return;
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}
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default: EXIT("unknown release_mem data selector: %" PRIu32 "\n", data_sel);
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}
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EXIT("unknown event type\n");
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}
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void CommandProcessor::WriteAtEndOfPipe32(uint32_t eop_event_type, uint32_t cache_action,
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uint32_t event_index, uint32_t event_write_source,
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void* dst_gpu_addr, uint32_t value,
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uint32_t interrupt_selector,
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uint32_t interrupt_context_id) {
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WriteAtEndOfPipe(eop_event_type, cache_action, event_index, event_write_source, dst_gpu_addr,
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value, interrupt_selector, interrupt_context_id);
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}
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void CommandProcessor::WriteAtEndOfPipe64(uint32_t eop_event_type, uint32_t cache_action,
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uint32_t event_index, uint32_t event_write_source,
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void* dst_gpu_addr, uint64_t value,
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uint32_t interrupt_selector,
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uint32_t interrupt_context_id) {
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WriteAtEndOfPipe(eop_event_type, cache_action, event_index, event_write_source, dst_gpu_addr,
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value, interrupt_selector, interrupt_context_id);
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}
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void CommandProcessor::TriggerEopEventAtEndOfPipe(uint32_t interrupt_context_id) {
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m_renderer.GetOcclusionQueries().Publish();
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(void)CurrentBuffer().Handle();
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GetScheduler().DeferPriorityOperation(
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[&renderer = m_renderer, event_id = m_interrupt_event_id, interrupt_context_id] {
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renderer.TriggerInterrupt(event_id, interrupt_context_id);
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});
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if (interrupt) {
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GetScheduler().DeferPriorityOperation(
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[&renderer = m_renderer, event_id = m_interrupt_event_id, interrupt_context_id] {
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renderer.TriggerInterrupt(event_id, interrupt_context_id);
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});
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BufferFlush();
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}
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}
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void CommandProcessor::TriggerEvent(uint32_t event_type, uint32_t event_index,
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@@ -1245,10 +1106,6 @@ void CommandProcessor::PrepareCpuFlip(uint64_t request_id) {
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GetScheduler().Flush();
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}
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void CommandProcessor::SynchronizeGpu() {
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GetScheduler().Finish();
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}
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bool GuestGpu::IsGpuThread() noexcept {
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return g_gpu_thread;
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}
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