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Decode unsigned byte sources for SDWA half-float conversion
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@@ -527,8 +527,8 @@ constexpr Vop1SdwaRule VOP1_SDWA_RULES[] = {
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{Opcode::V_CVT_F32_F16, SdwaSelWords() | SdwaSelFull(), 0, 0, true},
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{Opcode::V_CVT_F32_F16, SdwaSelWords() | SdwaSelFull(), 0, 0, true},
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{Opcode::V_CVT_F16_F32, SdwaSelBytes() | SdwaSelWords() | SdwaSelFull(), SdwaSelWords(),
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{Opcode::V_CVT_F16_F32, SdwaSelBytes() | SdwaSelWords() | SdwaSelFull(), SdwaSelWords(),
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SdwaSelBytes() | SdwaSelWords() | SdwaSelFull(), true},
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SdwaSelBytes() | SdwaSelWords() | SdwaSelFull(), true},
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{Opcode::V_CVT_F16_U16, SdwaSelWords() | SdwaSelFull(), SdwaSelWords(),
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{Opcode::V_CVT_F16_U16, SdwaSelBytes() | SdwaSelWords() | SdwaSelFull(), SdwaSelWords(),
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SdwaSelWords() | SdwaSelFull(), false},
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SdwaSelBytes() | SdwaSelWords() | SdwaSelFull(), false},
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{Opcode::V_CVT_U16_F16, SdwaSelWords() | SdwaSelFull(), SdwaSelWords(),
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{Opcode::V_CVT_U16_F16, SdwaSelWords() | SdwaSelFull(), SdwaSelWords(),
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SdwaSelWords() | SdwaSelFull(), true},
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SdwaSelWords() | SdwaSelFull(), true},
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{Opcode::V_CVT_F16_I16, SdwaSelWords() | SdwaSelFull(), SdwaSelWords(),
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{Opcode::V_CVT_F16_I16, SdwaSelWords() | SdwaSelFull(), SdwaSelWords(),
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@@ -618,13 +618,14 @@ bool SupportsVop1Clamp(Opcode opcode) {
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}
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}
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bool ValidateVop1Sdwa(Instruction& inst, uint32_t opcode, uint32_t modifier) {
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bool ValidateVop1Sdwa(Instruction& inst, uint32_t opcode, uint32_t modifier) {
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const auto dst_sel = (modifier >> 8u) & 0x7u;
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const auto dst_sel = (modifier >> 8u) & 0x7u;
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const auto dst_u = (modifier >> 11u) & 0x3u;
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const auto dst_u = (modifier >> 11u) & 0x3u;
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const auto clamp = (modifier >> 13u) & 0x1u;
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const auto clamp = (modifier >> 13u) & 0x1u;
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const auto omod = (modifier >> 14u) & 0x3u;
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const auto omod = (modifier >> 14u) & 0x3u;
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const auto src0_sel = (modifier >> 16u) & 0x7u;
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const auto src0_sel = (modifier >> 16u) & 0x7u;
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const auto src0_neg = (modifier >> 20u) & 0x1u;
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const auto src0_sext = (modifier >> 19u) & 0x1u;
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const auto src0_abs = (modifier >> 21u) & 0x1u;
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const auto src0_neg = (modifier >> 20u) & 0x1u;
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const auto src0_abs = (modifier >> 21u) & 0x1u;
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if (src0_sel > 6u || dst_sel > 6u) {
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if (src0_sel > 6u || dst_sel > 6u) {
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SetUnsupported(inst, Family::VOP1, opcode, "VOP1 SDWA selector is invalid");
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SetUnsupported(inst, Family::VOP1, opcode, "VOP1 SDWA selector is invalid");
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@@ -640,7 +641,8 @@ bool ValidateVop1Sdwa(Instruction& inst, uint32_t opcode, uint32_t modifier) {
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"VOP1 SDWA destination selector is not supported");
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"VOP1 SDWA destination selector is not supported");
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return false;
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return false;
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}
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}
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if (!IsVop1SdwaSourceSupported(inst.opcode, src0_sel, src0_neg != 0u, src0_abs != 0u)) {
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if (!IsVop1SdwaSourceSupported(inst.opcode, src0_sel, src0_neg != 0u, src0_abs != 0u) ||
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(inst.opcode == Opcode::V_CVT_F16_U16 && src0_sel <= 3u && src0_sext != 0u)) {
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SetUnsupported(inst, Family::VOP1, opcode, "VOP1 SDWA source selector is not supported");
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SetUnsupported(inst, Family::VOP1, opcode, "VOP1 SDWA source selector is not supported");
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return false;
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return false;
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}
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}
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@@ -19624,6 +19624,33 @@ TestCase VectorMinMaxF16Ops() {
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O::S_ENDPGM}};
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O::S_ENDPGM}};
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}
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}
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TestCase VectorCvtF16U16CapturedByteSource() {
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using O = ShaderOpcode;
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constexpr std::array inputs = {0xff123456u, 0x80123456u, 0x00123456u};
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std::vector<u32> code;
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AppendVMovLiteral(&code, 16, 0xa5a55a5au);
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for (u32 i = 0; i < inputs.size(); i++) {
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AppendVMovU32(&code, 30, i * 4u);
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AppendBufferLoadDword(&code, 18, 30);
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// Captured shader 0x15082e211725205f: unsigned byte3 -> FP16 word0,
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// preserving word1 of v16.
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code.insert(code.end(), {0x7e20a0f9u, 0x00031412u});
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AppendStoreVgpr(&code, 16, i);
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}
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AppendEnd(&code);
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TestCase test;
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test.name = "VectorCvtF16U16CapturedByteSource";
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test.code = std::move(code);
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test.initial.assign(inputs.begin(), inputs.end());
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test.expected = {0xa5a55bf8u, 0xa5a55800u, 0xa5a50000u};
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test.opcodes = {O::V_MOV_B32, O::BUFFER_LOAD_DWORD, O::V_CVT_F16_U16,
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O::BUFFER_STORE_DWORD, O::S_ENDPGM};
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test.required_spirv = {"OpBitFieldUExtract", "OpConvertUToF"};
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return test;
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}
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TestCase VectorCvtU16F16Sdwa() {
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TestCase VectorCvtU16F16Sdwa() {
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using O = ShaderOpcode;
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using O = ShaderOpcode;
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@@ -27458,6 +27485,7 @@ std::vector<TestCase> MakeCases() {
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AddCase(CvtPkrtzF16F32SdwaAndOutputModifiers);
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AddCase(CvtPkrtzF16F32SdwaAndOutputModifiers);
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AddCase(PackedMinMaxF16NanAndSignedZeroEdges);
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AddCase(PackedMinMaxF16NanAndSignedZeroEdges);
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AddCase(VectorMinMaxF16Ops);
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AddCase(VectorMinMaxF16Ops);
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AddCase(VectorCvtF16U16CapturedByteSource);
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AddCase(VectorCvtU16F16Sdwa);
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AddCase(VectorCvtU16F16Sdwa);
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AddCase(NativeAndSdwa16BitDestinationWrites);
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AddCase(NativeAndSdwa16BitDestinationWrites);
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AddCase(VectorMinMaxMed3F16Ops);
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AddCase(VectorMinMaxMed3F16Ops);
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@@ -3466,6 +3466,13 @@ void TestNewShaderRecompilerCapturedVop1SdwaByteConvert() {
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Check(SpirvContainsOpcode(result.spirv, 112),
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Check(SpirvContainsOpcode(result.spirv, 112),
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"captured SDWA byte conversion did not emit OpConvertUToF");
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"captured SDWA byte conversion did not emit OpConvertUToF");
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CheckSpirvBinaryValidates(result.spirv);
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CheckSpirvBinaryValidates(result.spirv);
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const uint32_t byte_sext[] = {0x7e20a0f9u, 0x000b1412u};
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ShaderRecompiler::Decoder::Instruction decoded;
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ShaderRecompiler::Decoder::DecodeInstruction(byte_sext, 0, decoded);
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Check(decoded.word_count == 2u &&
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decoded.opcode == ShaderRecompiler::Decoder::Opcode::UNSUPPORTED,
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"V_CVT_F16_U16 accepted unimplemented SDWA byte sign extension");
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}
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}
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void TestNewShaderRecompilerVop1SdwaNotDestination() {
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void TestNewShaderRecompilerVop1SdwaNotDestination() {
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