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graphics: emit PS5 register object and primitive IDs to RT7

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nmzik committed 2026-10-15 22:28:01 +02:00
1 parent d172ab75ca
commit f7226ca7dc
15 files changed
+291 -101
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src/graphics/guest_gpu/command_processor/pm4Handlers.cpp
+6 -20
View File
@@ -295,10 +295,6 @@ static void HwCtxIgnoreDisabledUserClipPlane(CommandProcessor& cp, uint32_t valu
EXIT_NOT_IMPLEMENTED(value != 0 || cp.GetCtx().GetClipControl().user_clip_planes != 0);
}
static void HwCtxIgnoreDrawPayloadControl([[maybe_unused]] uint32_t value) {}
static void HwCtxIgnoreObjprimIdControl([[maybe_unused]] uint32_t value) {}
static void HwCtxIgnorePrimitiveIdReset([[maybe_unused]] uint32_t value) {}
static void HwCtxIgnoreVtxControl([[maybe_unused]] uint32_t value) {}
@@ -454,23 +450,13 @@ KYTY_HW_CTX_PARSER(HwCtxSetAlphaToMask) {
}
KYTY_HW_CTX_PARSER(HwCtxSetDrawPayloadControl) {
auto num_values = KYTY_PM4_LEN(cmd_id) - 2u;
for (uint32_t i = 0; i < num_values; i++) {
HwCtxIgnoreDrawPayloadControl(buffer[i]);
}
return num_values;
cp.GetCtx().SetDrawPayloadControl(buffer[0]);
return KYTY_PM4_LEN(cmd_id) - 2u;
}
KYTY_HW_CTX_PARSER(HwCtxSetObjprimIdControl) {
auto num_values = KYTY_PM4_LEN(cmd_id) - 2u;
for (uint32_t i = 0; i < num_values; i++) {
HwCtxIgnoreObjprimIdControl(buffer[i]);
}
return num_values;
cp.GetCtx().SetObjprimIdControl(buffer[0]);
return KYTY_PM4_LEN(cmd_id) - 2u;
}
KYTY_HW_CTX_PARSER(HwCtxSetPrimitiveIdReset) {
@@ -3106,7 +3092,7 @@ void GraphicsInitJmpTablesCxIndirect() {
cp.GetCtx().SetTfParam(value);
};
g_hw_ctx_indirect_func[Pm4::VGT_DRAW_PAYLOAD_CNTL] = [](KYTY_HW_CTX_INDIRECT_ARGS) {
HwCtxIgnoreDrawPayloadControl(value);
cp.GetCtx().SetDrawPayloadControl(value);
};
g_hw_ctx_indirect_func[Pm4::VGT_PRIMITIVEID_RESET] = [](KYTY_HW_CTX_INDIRECT_ARGS) {
HwCtxIgnorePrimitiveIdReset(value);
@@ -3115,7 +3101,7 @@ void GraphicsInitJmpTablesCxIndirect() {
cp.GetCtx().SetShaderZFormat(value);
};
g_hw_ctx_indirect_func[Pm4::PA_CL_OBJPRIM_ID_CNTL] = [](KYTY_HW_CTX_INDIRECT_ARGS) {
HwCtxIgnoreObjprimIdControl(value);
cp.GetCtx().SetObjprimIdControl(value);
};
for (auto cmd_offset = Pm4::PA_SC_CLIPRECT_RULE; cmd_offset < Pm4::PA_SC_CLIPRECT_0_TL + 8u;
src/graphics/guest_gpu/hardwareContext.h
+8
View File
@@ -556,6 +556,8 @@ struct ShaderRegisters {
uint32_t m_vgtGsMaxVertOut = 0;
uint32_t m_vgtGsOutPrimType = 0;
uint32_t m_vgtPrimitiveIdEn = 0;
uint32_t m_vgtDrawPayloadCntl = 0;
uint32_t m_paClObjprimIdCntl = 0;
uint32_t m_vgtReuseOff = 0;
uint32_t m_vgtTessDistribution = 0;
uint32_t m_vgtLsHsConfig = 0;
@@ -679,6 +681,10 @@ public:
void SetRenderTargetMask(uint32_t mask) { m_render_target_mask = mask; }
[[nodiscard]] uint32_t GetRenderTargetMask() const { return m_render_target_mask; }
[[nodiscard]] bool HasObjectPrimitiveIdOutput() const {
return (m_sh_regs.m_vgtDrawPayloadCntl & 1u) != 0 &&
(m_render_target_mask & 0xf0000000u) != 0;
}
void SetShaderStages(uint32_t flags) { m_shader_stages = flags; }
[[nodiscard]] uint32_t GetShaderStages() const { return m_shader_stages; }
@@ -877,6 +883,8 @@ public:
void SetGsMaxVertOut(uint32_t value) { m_sh_regs.m_vgtGsMaxVertOut = value; }
void SetGsOutPrimType(uint32_t value) { m_sh_regs.m_vgtGsOutPrimType = value; }
void SetPrimitiveIdEn(uint32_t value) { m_sh_regs.m_vgtPrimitiveIdEn = value; }
void SetDrawPayloadControl(uint32_t value) { m_sh_regs.m_vgtDrawPayloadCntl = value; }
void SetObjprimIdControl(uint32_t value) { m_sh_regs.m_paClObjprimIdCntl = value; }
void SetReuseOff(uint32_t value) { m_sh_regs.m_vgtReuseOff = value; }
void SetTessDistribution(uint32_t value) { m_sh_regs.m_vgtTessDistribution = value; }
void SetLsHsConfig(uint32_t value) { m_sh_regs.m_vgtLsHsConfig = value; }