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78adb9293d5ea69a01fc3875a75289d055d772b6
Commit Graph
280 Commits
Author SHA1 Message Date
nmzikandshadowbeat070 78adb9293d shader: give A16 1D and late 3D gradients their own address VGPRs 
Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com>
 2026-10-27 04:23:01 +01:00
nmzikandshadowbeat070 04bfd9070c shader: give an A16 bias its own address VGPR 
Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com>
 2026-10-27 04:23:01 +01:00
nmzikandshadowbeat070 ffa3992c1a shader: decode every PS5 image_gather4 encoding 
Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com>
 2026-10-27 04:23:00 +01:00
nmzik 2483573651 shader: mask V_MAD_U64_U32 carry-out bits of lanes outside EXEC 2026-10-27 04:23:00 +01:00
MrFr3di 986721f5bc shader: decode FLAT, GLOBAL and SCRATCH D16 high-half loads (#1924) 
FLAT-family opcode 0x25 (FLAT/GLOBAL/SCRATCH_LOAD_SHORT_D16_HI) loads an
unsigned halfword into bits [31:16] of the destination and keeps bits [15:0].
Decode it beside the low-half variant and let it select the high half of the
existing partial destination write, so FLAT_LOAD needs no new path.

Ghost of Yotei CS 0x79b0066f0cd1f3cd stopped at
global_load_short_d16_hi v16, v18, s[0:1] offset:196 (0xdc9480c4 0x10000012).
 2026-10-26 22:34:54 +01:00
nmzikandSenaxx 943bc19f46 shader: leave the start instance out of mesh and NGG instance ID VGPRs 
Co-authored-by: Senaxx <michelbeld@gmail.com>
 2026-10-26 07:43:11 +01:00
nmzik 5429888d4c shader: keep pixel helper lanes out of the EXEC and VCC words 2026-10-26 07:43:11 +01:00
nmzikandSenaxx 025d1f7edf shader: decode the SHARED_LIMIT and PRIVATE_LIMIT inline constants 
Co-authored-by: Senaxx <michelbeld@gmail.com>
 2026-10-26 06:35:17 +01:00
nmzikandSenaxx 4ebae87a1b shader: apply the LOD clamp of image_sample _cl variants 
Co-authored-by: Senaxx <michelbeld@gmail.com>
 2026-10-26 05:32:02 +01:00
nmzikAli AlmohayaSenaxxMac
 		7524e8f79e shader: count one SGPR for lane reads and wave32 lane masks in call targets 
Co-authored-by: Ali Almohaya <AliAlmohaya@gmail.com>
Co-authored-by: Senaxx <michelbeld@gmail.com>
Co-authored-by: Mac <me@itsmemac.com>
 2026-10-26 05:32:02 +01:00
nmzik 153dadd0b3 shader: emit 16-bit packs with a zero high lane as a mask 2026-10-26 05:32:02 +01:00
nmzik 67c89e0915 shader: keep the old V_PERMLANE16 destination for inactive sources without BOUND_CTRL 2026-10-25 02:20:44 +02:00
TheCruZ e864cb20bd shader: clamp V_FRACT_F16/F32/F64 results below one 2026-10-25 02:20:44 +02:00
TheCruZ 9210264d47 shader: saturate V_CVT_PK_U16_U32 and V_CVT_PK_I16_I32 2026-10-25 02:20:44 +02:00
Senaxx 77a8f30758 shader: read S_MEMREALTIME from the host device clock shifted to about 100 MHz 2026-10-23 19:48:53 +02:00
nmzik ecc30a1f2d shader: decode S_FLBIT_I32 and S_FLBIT_I32_I64 with a 4-op signed leading-bit search 2026-10-23 19:48:53 +02:00
Felipe 9dcff95e80 shader: fix crash from packed ancillary used as DPP old operand (#1769) 
shader: emit plain EXEC selects for DPP writes that reach every active lane (Street Fighter 6)
 2026-10-23 09:51:32 +02:00
nmzik c5016d9455 shader: support D16 XY and XYZ formatted buffer loads and stores 2026-10-22 05:26:54 +02:00
nmzik 753f285198 shader: generalize D16 buffer format component handling 2026-10-22 05:26:54 +02:00
Nawid3333andnmzik d7c1896647 shader: interpolate f16 parameter halves (V_INTERP_P1LL_F16, V_INTERP_P2_F16) (#1792) 
shader: interpolate packed f16 attributes for v_interp_p1ll_f16 and v_interp_p2_f16

Co-authored-by: nmzik <Nmzik@mail.ru>
 2026-10-22 04:54:10 +02:00
nmzik 6ee2ef8715 shader: insert the V_CVT_PK_U8_F32 byte with one bit-field insert 2026-10-22 00:31:52 +02:00
nmzik 9e4234cdbe shader: extract the V_CVT_F32_UBYTE source byte with one bit-field extract 2026-10-22 00:30:39 +02:00
nmzik 2d00e13bf3 shader: rely on the saturating float-to-int conversion instead of re-saturating in the translator 2026-10-22 00:26:40 +02:00
nmzik 9c39062d3e shader: double the cube major axis once after selecting the face 2026-10-21 23:56:13 +02:00
nmzik da19501889 shader: translate zero-kind branches as the negated nonzero vote 2026-10-21 23:33:30 +02:00
nmzik ae47ac26e7 shader: compute scalar signed-overflow SCC with compares instead of XOR masks 2026-10-21 23:27:04 +02:00
nmzik 7c40dbc36c shader: build the S_BFE_U64 mask from clamped halves and remove RightMask64 2026-10-21 23:16:17 +02:00
nmzik 0cdc5c1224 shader: build the V_MBCNT lanes-below mask with the shared right-mask helper 2026-10-21 23:11:26 +02:00
nmzik fa32940d14 shader: drop BFM mask bits shifted past bit 31 instead of an out-of-range bit-field insert 2026-10-21 22:59:56 +02:00
nmzik 2862ad5b25 shader: compute scalar signed-overflow and shift-add carry SCC with fewer ops 2026-10-21 22:56:21 +02:00
nmzik aacf15fd0b shader: write preserved SDWA fields with one bit-field insert and drop duplicate 16-bit masks 2026-10-21 22:52:14 +02:00
nmzik 10a852c2ac shader: pack 16-bit lane pairs with one bit-field insert 2026-10-21 22:46:04 +02:00
nmzik 4a1440197f shader: share one find-first-bit lowering for S_FF0/FF1/FLBIT_I32_B64 and remove FindUMsb64 2026-10-21 22:39:34 +02:00
nmzik 6e5167598e shader: compute add-with-carry with compares and remove IAddCarry32 2026-10-21 22:28:11 +02:00
nmzik c571d8ed5a shader: remove IR opcodes and IREmitter helpers that nothing produces 2026-10-21 22:19:26 +02:00
nmzik 63ca9c0b80 shader: decode PS5 image_gather4_c_a and image_gather4_c_o_a 2026-10-20 15:21:19 +02:00
Mr. Big Britches 4a2961cdf9 shader: reflect tessellation strides across forward branches, DS write widths, and packed patch masks 2026-10-20 15:21:19 +02:00
Andre Michi 1a053f9e13 shader: accept dword SETPC tables whose load reuses the selector 2026-10-20 05:11:48 +02:00
nmzik f186b35706 shader: drop null checks on the stage input info pointers 2026-10-20 03:22:40 +02:00
nmzik ab8566591f shader: link multiple compute helpers without synthetic return loops 2026-10-19 02:34:25 +02:00
nmzik 22ef16a044 shader: implement PS5 vector data cache invalidation 2026-10-18 15:57:14 +02:00
Nawid3333andClaude Opus 5.5 b82512be06 shader: read float inline constants on 64-bit operands as f64 bits (#1576) 
A float inline constant (240-248) read by a 64-bit operand is the f64 bit
pattern for integer B64 opcodes too: AMD's compilers emit
v_lshrrev_b64 v[4:5], v0, 1.0 for 0x3ff0000000000000 >> lane. ReadU32Pair
returned {f32 bits, 0}, so only F64-typed reads had the right value.

Based on TheCruZ's 284deab28 (closed #1219).

Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>
 2026-10-17 05:21:06 +02:00
Nawid3333andClaude Opus 5.5 ba8b0c85b8 shader: keep quiet NaNs with payload bits out of the packed f16 min/max sNaN path (#1579) 
V_PK_MIN_F16 and V_PK_MAX_F16 return the quieted NaN for a signaling NaN
operand and the other operand for a quiet one (per half, as V_MIN_F16 and
V_MAX_F16 do). The signaling test masked the half with 0x7c00 and checked
for a nonzero payload, so a quiet NaN with payload bits such as 0x7e01 was
taken as signaling and returned. Mask with 0x7e00 so the quiet bit must be
clear.

Two more vectors in PackedMinMaxF16NanAndSignedZeroEdges cover it.

Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>
 2026-10-17 05:12:37 +02:00
Nawid3333andClaude Opus 5.5 b6bd9ecae4 shader: read float inline constants on 16-bit operands as half bits (#1582) 
The 16-bit encodings of the float inline constants are fixed: the exact
halves of 0.5, 1.0, 2.0 and 4.0 and their negations, and 0x3118 for
1/(2*pi). Read16LaneBits converted the 32-bit value at run time instead,
through PackHalf2x16, which the AMD driver rounds toward zero, so
1/(2*pi) became 0x3117. Use the encodings directly.

Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>
 2026-10-17 05:05:40 +02:00
Nawid3333Claude Opus 5.5nmzik
 		e93b4b0378 shader: support returning 32-bit LDS compare-exchange (DS_CMPST_RTN_B32) (#1578) 
* shader: support DS_CMPST_RTN_B32

Assassin's Creed Valhalla (PPSA01490, #281) stops on DS opcode 0x30 in a
compute shader. DS compares DATA and stores DATA2, the opposite of
BUFFER_ATOMIC_CMPSWAP, so the 32-bit atomic path swaps the two for this
opcode, as the 64-bit form does.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

* shader: reject unsupported GDS compare-store variant

---------

Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>
Co-authored-by: nmzik <Nmzik@mail.ru>
 2026-10-17 04:37:16 +02:00
Çağatay Güçlü 02ead0e2e1 shader: 64-bit buffer atomic add (BUFFER_ATOMIC_ADD_X2) 2026-10-17 04:09:54 +02:00
nmzik c8caa27936 shader: preserve folded native constants for descriptor provenance 2026-10-15 23:22:30 +02:00
nmzikandfxpw dd429ef858 shader: decode high-half formatted buffer stores 
Co-authored-by: fxpw <fxpw@outlook.com>
 2026-10-15 22:28:00 +02:00
nmzikandfxpw bc2664cefa shader: decode comparison gathers with explicit LOD 
Co-authored-by: fxpw <fxpw@outlook.com>
 2026-10-15 22:28:00 +02:00
nmzikandfxpw 2f6ee0e91d shader: support RDNA2 high-half short buffer stores 
Co-authored-by: fxpw <fxpw@outlook.com>
 2026-10-14 20:55:50 +02:00