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1,680 Commits 2 Branches 522 Tags
9210264d4761e1e02cc4db1241fd76a970660041
Commit Graph
196 Commits
Author SHA1 Message Date
TheCruZ 9210264d47 shader: saturate V_CVT_PK_U16_U32 and V_CVT_PK_I16_I32 2026-10-25 02:20:44 +02:00
Senaxx 77a8f30758 shader: read S_MEMREALTIME from the host device clock shifted to about 100 MHz 2026-10-23 19:48:53 +02:00
nmzik ecc30a1f2d shader: decode S_FLBIT_I32 and S_FLBIT_I32_I64 with a 4-op signed leading-bit search 2026-10-23 19:48:53 +02:00
Felipe 9dcff95e80 shader: fix crash from packed ancillary used as DPP old operand (#1769) 
shader: emit plain EXEC selects for DPP writes that reach every active lane (Street Fighter 6)
 2026-10-23 09:51:32 +02:00
nmzik c5016d9455 shader: support D16 XY and XYZ formatted buffer loads and stores 2026-10-22 05:26:54 +02:00
nmzik 753f285198 shader: generalize D16 buffer format component handling 2026-10-22 05:26:54 +02:00
Nawid3333andnmzik d7c1896647 shader: interpolate f16 parameter halves (V_INTERP_P1LL_F16, V_INTERP_P2_F16) (#1792) 
shader: interpolate packed f16 attributes for v_interp_p1ll_f16 and v_interp_p2_f16

Co-authored-by: nmzik <Nmzik@mail.ru>
 2026-10-22 04:54:10 +02:00
nmzik 6ee2ef8715 shader: insert the V_CVT_PK_U8_F32 byte with one bit-field insert 2026-10-22 00:31:52 +02:00
nmzik 9e4234cdbe shader: extract the V_CVT_F32_UBYTE source byte with one bit-field extract 2026-10-22 00:30:39 +02:00
nmzik 2d00e13bf3 shader: rely on the saturating float-to-int conversion instead of re-saturating in the translator 2026-10-22 00:26:40 +02:00
nmzik 9c39062d3e shader: double the cube major axis once after selecting the face 2026-10-21 23:56:13 +02:00
nmzik da19501889 shader: translate zero-kind branches as the negated nonzero vote 2026-10-21 23:33:30 +02:00
nmzik ae47ac26e7 shader: compute scalar signed-overflow SCC with compares instead of XOR masks 2026-10-21 23:27:04 +02:00
nmzik 7c40dbc36c shader: build the S_BFE_U64 mask from clamped halves and remove RightMask64 2026-10-21 23:16:17 +02:00
nmzik 0cdc5c1224 shader: build the V_MBCNT lanes-below mask with the shared right-mask helper 2026-10-21 23:11:26 +02:00
nmzik fa32940d14 shader: drop BFM mask bits shifted past bit 31 instead of an out-of-range bit-field insert 2026-10-21 22:59:56 +02:00
nmzik 2862ad5b25 shader: compute scalar signed-overflow and shift-add carry SCC with fewer ops 2026-10-21 22:56:21 +02:00
nmzik aacf15fd0b shader: write preserved SDWA fields with one bit-field insert and drop duplicate 16-bit masks 2026-10-21 22:52:14 +02:00
nmzik 10a852c2ac shader: pack 16-bit lane pairs with one bit-field insert 2026-10-21 22:46:04 +02:00
nmzik 4a1440197f shader: share one find-first-bit lowering for S_FF0/FF1/FLBIT_I32_B64 and remove FindUMsb64 2026-10-21 22:39:34 +02:00
nmzik 6e5167598e shader: compute add-with-carry with compares and remove IAddCarry32 2026-10-21 22:28:11 +02:00
nmzik c571d8ed5a shader: remove IR opcodes and IREmitter helpers that nothing produces 2026-10-21 22:19:26 +02:00
nmzik f186b35706 shader: drop null checks on the stage input info pointers 2026-10-20 03:22:40 +02:00
nmzik 22ef16a044 shader: implement PS5 vector data cache invalidation 2026-10-18 15:57:14 +02:00
Nawid3333andClaude Opus 5.5 b82512be06 shader: read float inline constants on 64-bit operands as f64 bits (#1576) 
A float inline constant (240-248) read by a 64-bit operand is the f64 bit
pattern for integer B64 opcodes too: AMD's compilers emit
v_lshrrev_b64 v[4:5], v0, 1.0 for 0x3ff0000000000000 >> lane. ReadU32Pair
returned {f32 bits, 0}, so only F64-typed reads had the right value.

Based on TheCruZ's 284deab28 (closed #1219).

Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>
 2026-10-17 05:21:06 +02:00
Nawid3333andClaude Opus 5.5 ba8b0c85b8 shader: keep quiet NaNs with payload bits out of the packed f16 min/max sNaN path (#1579) 
V_PK_MIN_F16 and V_PK_MAX_F16 return the quieted NaN for a signaling NaN
operand and the other operand for a quiet one (per half, as V_MIN_F16 and
V_MAX_F16 do). The signaling test masked the half with 0x7c00 and checked
for a nonzero payload, so a quiet NaN with payload bits such as 0x7e01 was
taken as signaling and returned. Mask with 0x7e00 so the quiet bit must be
clear.

Two more vectors in PackedMinMaxF16NanAndSignedZeroEdges cover it.

Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>
 2026-10-17 05:12:37 +02:00
Nawid3333andClaude Opus 5.5 b6bd9ecae4 shader: read float inline constants on 16-bit operands as half bits (#1582) 
The 16-bit encodings of the float inline constants are fixed: the exact
halves of 0.5, 1.0, 2.0 and 4.0 and their negations, and 0x3118 for
1/(2*pi). Read16LaneBits converted the 32-bit value at run time instead,
through PackHalf2x16, which the AMD driver rounds toward zero, so
1/(2*pi) became 0x3117. Use the encodings directly.

Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>
 2026-10-17 05:05:40 +02:00
Nawid3333Claude Opus 5.5nmzik
 		e93b4b0378 shader: support returning 32-bit LDS compare-exchange (DS_CMPST_RTN_B32) (#1578) 
* shader: support DS_CMPST_RTN_B32

Assassin's Creed Valhalla (PPSA01490, #281) stops on DS opcode 0x30 in a
compute shader. DS compares DATA and stores DATA2, the opposite of
BUFFER_ATOMIC_CMPSWAP, so the 32-bit atomic path swaps the two for this
opcode, as the 64-bit form does.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

* shader: reject unsupported GDS compare-store variant

---------

Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>
Co-authored-by: nmzik <Nmzik@mail.ru>
 2026-10-17 04:37:16 +02:00
Çağatay Güçlü 02ead0e2e1 shader: 64-bit buffer atomic add (BUFFER_ATOMIC_ADD_X2) 2026-10-17 04:09:54 +02:00
nmzik c8caa27936 shader: preserve folded native constants for descriptor provenance 2026-10-15 23:22:30 +02:00
nmzikandfxpw dd429ef858 shader: decode high-half formatted buffer stores 
Co-authored-by: fxpw <fxpw@outlook.com>
 2026-10-15 22:28:00 +02:00
nmzikandfxpw bc2664cefa shader: decode comparison gathers with explicit LOD 
Co-authored-by: fxpw <fxpw@outlook.com>
 2026-10-15 22:28:00 +02:00
nmzikandfxpw 2f6ee0e91d shader: support RDNA2 high-half short buffer stores 
Co-authored-by: fxpw <fxpw@outlook.com>
 2026-10-14 20:55:50 +02:00
nmzikandfxpw 4843d8d942 shader: support packed D16 XYZW formatted buffer stores 
Co-authored-by: fxpw <fxpw@outlook.com>
 2026-10-14 19:35:08 +02:00
nmzikandfxpw e0586cc85a shader: decode unsigned byte loads into preserved low halves 
Co-authored-by: fxpw <fxpw@outlook.com>
 2026-10-14 18:21:58 +02:00
nmzikandfxpw 8d18be71db shader: decode upper-half byte stores through shared operand selection 
Co-authored-by: fxpw <fxpw@outlook.com>
 2026-10-14 04:20:02 +02:00
nmzikandfxpw 6abfe3bbe4 shader: share formatted loads and support packed D16 XYZW buffers 
Co-authored-by: fxpw <fxpw@outlook.com>
 2026-10-14 04:09:57 +02:00
nmzik 9e41d8320a shader: support returning 64-bit LDS max and compare-exchange 2026-10-13 21:33:50 +00:00
nmzikandnetwarex 984cfcebd1 shader: emit native texel offsets using sample execution context 
Co-authored-by: netwarex <mail@pety.me>
 2026-10-11 18:53:01 +02:00
nmzik cf77fb4353 shader: initialize NGG vertex count from active native invocations 2026-10-11 01:05:56 +02:00
Mac 679be25c37 shader: recognize remaining disabled debug branches 2026-10-10 04:31:55 +02:00
fxpw fa56c5eae9 shader: add scalar zero-bit count and search operations 2026-10-10 04:31:55 +02:00
TheCruZ d247d3d60c shader: complete signed 64-bit integer comparisons 2026-10-10 03:36:25 +02:00
nmzikandHector Mödinger S. 59183dbfa8 shader: add missing F64 VOPC compares 
Co-authored-by: Hector Mödinger S. <hectormodinger@gmail.com>
 2026-10-09 21:01:51 +02:00
nmzik bb5edbd490 shader: expose graphics compute queue fields to GETREG 2026-10-09 15:06:39 +00:00
nmzikandBehzad 1818aae562 shader: link scalar leaf calls only for SWAPPC programs 
Co-authored-by: Behzad <behzadkhan1736@gmail.com>
 2026-10-09 15:06:39 +00:00
nmzik a31e2cd361 shader: BUFFER_LOAD_SHORT_D16_HI 2026-10-09 12:57:04 +02:00
nmzik 1bd282ec0a shader: BUFFER_LOAD_SHORT_D16 2026-10-09 12:57:04 +02:00
nmzik 3df456675d shader: own control flow on IR blocks with direct targets 2026-10-09 01:59:41 +02:00
shadowbeat070 7881c69a54 shader: decode v_cmp_class_f16 2026-10-08 01:10:49 +04:00