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ba8b0c85b80e74de092c410f625a496831d18ead
Commit Graph
171 Commits
Author SHA1 Message Date
Nawid3333andClaude Opus 5.5 ba8b0c85b8 shader: keep quiet NaNs with payload bits out of the packed f16 min/max sNaN path (#1579) 
V_PK_MIN_F16 and V_PK_MAX_F16 return the quieted NaN for a signaling NaN
operand and the other operand for a quiet one (per half, as V_MIN_F16 and
V_MAX_F16 do). The signaling test masked the half with 0x7c00 and checked
for a nonzero payload, so a quiet NaN with payload bits such as 0x7e01 was
taken as signaling and returned. Mask with 0x7e00 so the quiet bit must be
clear.

Two more vectors in PackedMinMaxF16NanAndSignedZeroEdges cover it.

Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>
 2026-10-17 05:12:37 +02:00
Nawid3333andClaude Opus 5.5 b6bd9ecae4 shader: read float inline constants on 16-bit operands as half bits (#1582) 
The 16-bit encodings of the float inline constants are fixed: the exact
halves of 0.5, 1.0, 2.0 and 4.0 and their negations, and 0x3118 for
1/(2*pi). Read16LaneBits converted the 32-bit value at run time instead,
through PackHalf2x16, which the AMD driver rounds toward zero, so
1/(2*pi) became 0x3117. Use the encodings directly.

Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>
 2026-10-17 05:05:40 +02:00
Nawid3333Claude Opus 5.5nmzik
 		e93b4b0378 shader: support returning 32-bit LDS compare-exchange (DS_CMPST_RTN_B32) (#1578) 
* shader: support DS_CMPST_RTN_B32

Assassin's Creed Valhalla (PPSA01490, #281) stops on DS opcode 0x30 in a
compute shader. DS compares DATA and stores DATA2, the opposite of
BUFFER_ATOMIC_CMPSWAP, so the 32-bit atomic path swaps the two for this
opcode, as the 64-bit form does.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

* shader: reject unsupported GDS compare-store variant

---------

Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>
Co-authored-by: nmzik <Nmzik@mail.ru>
 2026-10-17 04:37:16 +02:00
Çağatay Güçlü 02ead0e2e1 shader: 64-bit buffer atomic add (BUFFER_ATOMIC_ADD_X2) 2026-10-17 04:09:54 +02:00
nmzik c8caa27936 shader: preserve folded native constants for descriptor provenance 2026-10-15 23:22:30 +02:00
nmzikandfxpw dd429ef858 shader: decode high-half formatted buffer stores 
Co-authored-by: fxpw <fxpw@outlook.com>
 2026-10-15 22:28:00 +02:00
nmzikandfxpw bc2664cefa shader: decode comparison gathers with explicit LOD 
Co-authored-by: fxpw <fxpw@outlook.com>
 2026-10-15 22:28:00 +02:00
nmzikandfxpw 2f6ee0e91d shader: support RDNA2 high-half short buffer stores 
Co-authored-by: fxpw <fxpw@outlook.com>
 2026-10-14 20:55:50 +02:00
nmzikandfxpw 4843d8d942 shader: support packed D16 XYZW formatted buffer stores 
Co-authored-by: fxpw <fxpw@outlook.com>
 2026-10-14 19:35:08 +02:00
nmzikandfxpw e0586cc85a shader: decode unsigned byte loads into preserved low halves 
Co-authored-by: fxpw <fxpw@outlook.com>
 2026-10-14 18:21:58 +02:00
nmzikandfxpw 8d18be71db shader: decode upper-half byte stores through shared operand selection 
Co-authored-by: fxpw <fxpw@outlook.com>
 2026-10-14 04:20:02 +02:00
nmzikandfxpw 6abfe3bbe4 shader: share formatted loads and support packed D16 XYZW buffers 
Co-authored-by: fxpw <fxpw@outlook.com>
 2026-10-14 04:09:57 +02:00
nmzik 9e41d8320a shader: support returning 64-bit LDS max and compare-exchange 2026-10-13 21:33:50 +00:00
nmzikandnetwarex 984cfcebd1 shader: emit native texel offsets using sample execution context 
Co-authored-by: netwarex <mail@pety.me>
 2026-10-11 18:53:01 +02:00
nmzik cf77fb4353 shader: initialize NGG vertex count from active native invocations 2026-10-11 01:05:56 +02:00
Mac 679be25c37 shader: recognize remaining disabled debug branches 2026-10-10 04:31:55 +02:00
fxpw fa56c5eae9 shader: add scalar zero-bit count and search operations 2026-10-10 04:31:55 +02:00
TheCruZ d247d3d60c shader: complete signed 64-bit integer comparisons 2026-10-10 03:36:25 +02:00
nmzikandHector Mödinger S. 59183dbfa8 shader: add missing F64 VOPC compares 
Co-authored-by: Hector Mödinger S. <hectormodinger@gmail.com>
 2026-10-09 21:01:51 +02:00
nmzik bb5edbd490 shader: expose graphics compute queue fields to GETREG 2026-10-09 15:06:39 +00:00
nmzikandBehzad 1818aae562 shader: link scalar leaf calls only for SWAPPC programs 
Co-authored-by: Behzad <behzadkhan1736@gmail.com>
 2026-10-09 15:06:39 +00:00
nmzik a31e2cd361 shader: BUFFER_LOAD_SHORT_D16_HI 2026-10-09 12:57:04 +02:00
nmzik 1bd282ec0a shader: BUFFER_LOAD_SHORT_D16 2026-10-09 12:57:04 +02:00
nmzik 3df456675d shader: own control flow on IR blocks with direct targets 2026-10-09 01:59:41 +02:00
shadowbeat070 7881c69a54 shader: decode v_cmp_class_f16 2026-10-08 01:10:49 +04:00
shadowbeat070 9e666e4dd2 shader: support scalar byte sign extension 2026-10-08 01:10:49 +04:00
Claxten 5297abb7ac shader: run non-amplifying NGG programs in mesh workgroups 2026-10-07 21:17:35 +04:00
Claxten 3ba6ebae81 shader: initialize perspective sample barycentrics at SampleId 2026-10-07 20:44:46 +04:00
nmzik 96eb681b90 shader: add V_MIN3_U16 opcode 2026-10-07 16:22:30 +04:00
nmzik 26cce9909a shader: add BUFFER_LOAD_FORMAT_D16_X opcode 2026-10-07 16:22:30 +04:00
nmzik 5af370c257 shader: add BUFFER_STORE_FORMAT_D16_X opcode 2026-10-07 16:22:30 +04:00
nmzik bb98f26433 shader: add missing I64/U64 compare variants 2026-10-07 05:03:09 +04:00
NeySlimandnmzik 7492cb9577 shader: emulate DS_ORDERED_COUNT as a GDS atomic (#1117) 
* feat(shader): emulate DS_ORDERED_COUNT as a GDS atomic

* fix(shader): issue one ordered-count atomic per wave

* shader: correct ordered-count addressing and wave results

Use the M0 base and pixel packer offset for the GDS counter. Broadcast the
previous value to every lane and preserve the counter when EXEC is empty.

Add GPU regressions for add/exchange with full, partial, and empty EXEC in
wave32 and wave64. The targeted DS and buffer atomic suite passes 63 cases.

---------

Co-authored-by: nmzik <Nmzik@mail.ru>
 2026-10-07 01:45:37 +04:00
NeySlim 1195af2510 decoder: add V_CMPX_U_F32 (#1120) 
feat(decoder): add V_CMPX_U_F32
 2026-10-07 01:16:23 +04:00
Claxten 5601861d67 shader: implement RDNA2 scalar 16-bit sign extension 2026-10-06 14:53:17 +04:00
Claxten 9caec9f2c8 shader: preserve RDNA2 DLC coherence for flat address loads 2026-10-06 14:53:17 +04:00
nmzik 5b826c6e4a shader: emit native 64-bit operations where compatible 2026-10-05 20:41:03 +04:00
nmzik 7a0e1dafd7 shader: classify native half values with shared operand decoding 2026-10-05 18:39:31 +04:00
fxpw 1d55272467 shader: support V_CMPX_NE_U16 2026-10-05 09:25:19 +04:00
nmzik 2b1b7ed0e4 shader: FLAT opcode=0x24 2026-10-05 08:48:20 +04:00
nmzikandshadowbeat070 af3011cd69 shader: add missing 64-bit integer image atomics 
Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com>
 2026-10-05 04:12:06 +04:00
nmzikandshadowbeat070 d8be245c22 shader: separate legacy FP32 MAD rounding from fused FMA 
Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com>
 2026-10-05 04:11:48 +04:00
nmzikandÇağatay Güçlü 8274e517b2 shader: add FP64 min, max and rounding 
Co-authored-by: Çağatay Güçlü <33038942+defektu@users.noreply.github.com>
 2026-10-05 02:24:51 +04:00
nmzikandshadowbeat070 98557a83b6 shader: implement RDNA2 DS masked OR through shared atomic updates 
Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com>
 2026-10-04 18:39:34 +04:00
nmzik efbaa17f71 shader: preserve raw EXEC and VCC bits in 64-bit scalar selects 2026-10-04 18:39:34 +04:00
nmzik dbf66b7f4f shader: support RDNA2 BVH64 ray intersections with shared traversal 2026-10-04 18:39:34 +04:00
nmzikandshadowbeat070 c17fa5b936 shader: implement RDNA2 DS forward lane permute 
Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com>
 2026-10-04 18:39:34 +04:00
nmzik b8946fef94 shader: translate RDNA2 signed 64-bit not-equal comparisons 2026-10-04 18:39:34 +04:00
nmzikshadowbeat070TheCruZ
 		f18679e0cd shader: mask ALIGNBYTE offsets to the two-bit selector 
Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com>
Co-authored-by: TheCruZ <thecruzwtf@gmail.com>
 2026-10-04 18:39:34 +04:00
nmzik 284d58d1d5 shader: implement RDNA2 double-precision fractional part 2026-10-04 18:39:34 +04:00