Claxten a3ac6d0d32 shader: bound table keys by an inclusive guard with a constant limit

2026-10-27 04:23:00 +01:00

..

backend/spirv

shader: keep pixel helper lanes out of the EXEC and VCC words

2026-10-26 07:43:11 +01:00

frontend

shader: mask V_MAD_U64_U32 carry-out bits of lanes outside EXEC

2026-10-27 04:23:00 +01:00

ir

shader: bound table keys by an inclusive guard with a constant limit

2026-10-27 04:23:00 +01:00

BufferFormat.h

shader: decode buffer formats once

2026-09-08 21:26:59 +04:00

ShaderRecompiler.cpp

shader: count one SGPR for lane reads and wave32 lane masks in call targets

2026-10-26 05:32:02 +01:00

ShaderRecompiler.h

shader: count one SGPR for lane reads and wave32 lane masks in call targets

2026-10-26 05:32:02 +01:00

Tessellation.cpp

shader: drop the unread F32Class bits and the per-pass HS reflection counter reset

2026-10-20 23:54:32 +02:00

Tessellation.h

gpu: isolate tessellation analysis and SPIR-V emission

2026-09-14 06:58:32 +04:00