mirror of
https://github.com/KytyPS5/KytyPS5.git
synced 2026-10-27 16:02:37 +00:00
gpu emulation: remove unnecessary Vulkan synchronization
This commit is contained in:
nmzik committed
1 parent
ec78afb966
commit
1d5f3c8f66
3 files changed
+183
-43
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@@ -2682,14 +2682,21 @@ KYTY_CP_OP_PARSER(CpOpReleaseMem) {
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const bool gl2_writeback = ((gcr_cntl & GcrGl2Writeback) != 0);
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auto trigger_interrupt = [&]() {
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bool queued = false;
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switch (interrupt_selector) {
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case 0x00:
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case 0x03: break;
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case 0x01:
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case 0x02:
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case 0x04: cp.TriggerEopEventAtEndOfPipe(interrupt_context_id); break;
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case 0x04:
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cp.TriggerEopEventAtEndOfPipe(interrupt_context_id);
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queued = true;
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break;
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default: EXIT("unknown release_mem interrupt selector\n");
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}
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if (queued) {
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cp.BufferFlush();
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}
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};
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if (data_sel == 0 || interrupt_selector == 4) {
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@@ -2697,10 +2704,6 @@ KYTY_CP_OP_PARSER(CpOpReleaseMem) {
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cp.EmitGlobalBarrier();
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}
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if (gl2_writeback) {
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cp.SynchronizeGpu();
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}
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trigger_interrupt();
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return 7;
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@@ -2711,10 +2714,6 @@ KYTY_CP_OP_PARSER(CpOpReleaseMem) {
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cp.EmitGlobalBarrier();
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}
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if (gl2_writeback) {
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cp.SynchronizeGpu();
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}
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trigger_interrupt();
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return 7;
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@@ -2728,17 +2727,6 @@ KYTY_CP_OP_PARSER(CpOpReleaseMem) {
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cache_policy = 0;
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if (data_sel == 1) {
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static std::atomic<uint32_t> log_count {0};
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const auto dst_addr = reinterpret_cast<uint64_t>(dst_gpu_addr);
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if ((dst_addr & 0xffffffffff000000ull) == 0x0000001021000000ull || log_count.load() < 64) {
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if (log_count.fetch_add(1) < 256) {
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LOGF(
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"\t runtime release_mem32: dst=0x%016" PRIx64 ", value=0x%08" PRIx32
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", action=0x%02" PRIx32 ", gcr=0x%04" PRIx32 ", cache_action=0x%08" PRIx32 "\n",
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dst_addr, static_cast<uint32_t>(value), eop_event_type, gcr_cntl, cache_action);
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}
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}
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eop_event_type = 0x2f;
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event_index = 6;
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auto event_source = 2u;
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@@ -2753,7 +2741,6 @@ KYTY_CP_OP_PARSER(CpOpReleaseMem) {
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if (data_sel == 5) {
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if (gl2_writeback) {
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cp.SynchronizeGpu();
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cache_action = 0;
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}
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@@ -2764,7 +2751,9 @@ KYTY_CP_OP_PARSER(CpOpReleaseMem) {
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cp.WriteAtEndOfPipe32(cache_policy, event_write_dest, eop_event_type, cache_action,
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event_index, event_source, dst_gpu_addr, static_cast<uint32_t>(value),
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interrupt_selector, interrupt_context_id);
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cp.BufferFlush();
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if (interrupt_selector == 0x01) {
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cp.BufferFlush();
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}
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return 7;
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}
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@@ -124,7 +124,6 @@ private:
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uint64_t flip_request_id = 0;
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};
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void WaitLocked();
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void Enqueue(Submission submission);
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void WaitForIdle();
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void ProcessCommands();
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@@ -276,10 +275,8 @@ void GpuState::SubmitFlipPreparation(uint64_t request_id) {
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void GpuState::Done() {
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GpuMutexLock lock(m_submission_mutex);
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if (IsGpuThread()) {
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m_gfx_cp->BufferWait();
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} else {
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WaitLocked();
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if (!IsGpuThread()) {
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WaitForIdle();
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}
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m_graphics_done = true;
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m_done_num++;
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@@ -289,11 +286,6 @@ int GpuState::GetFrameNum() {
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return m_done_num;
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}
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void GpuState::WaitLocked() {
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WaitForIdle();
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SendCommandSync([this] { m_gfx_cp->BufferWait(); });
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}
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CommandProcessor& GpuState::GetProcessor(uint32_t queue_id) {
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EXIT_IF(queue_id >= QueueCount);
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if (queue_id == 0) {
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@@ -307,8 +299,6 @@ CommandProcessor& GpuState::GetProcessor(uint32_t queue_id) {
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}
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void CommandProcessor::Reset() {
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BufferWait();
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m_sh_ctx.Reset();
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m_ucfg.Reset();
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m_ctx.Reset();
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@@ -385,7 +375,6 @@ void CommandProcessor::WaitDeDiff(uint32_t diff) {
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}
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void CommandProcessor::IncrementDe() {
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BufferWait();
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m_de_count++;
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}
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@@ -1352,6 +1341,9 @@ void CommandProcessor::WriteAtEndOfPipe(uint32_t cache_policy, uint32_t event_wr
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value >> 16u);
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Sync::WriteAtEndOfPipeGds32(m_submit_id, CurrentBuffer(), dst, value & 0xffffu,
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value >> 16u);
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if (with_interrupt) {
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m_renderer.TriggerEopEvent(interrupt_context_id);
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}
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return;
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}
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} else if (eop_event_type == 0x04 && cache_action == 0x00 && event_index == 0x05) {
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@@ -1554,7 +1546,6 @@ void CommandProcessor::TriggerEvent(uint32_t event_type, uint32_t event_index) {
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event_index);
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}
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EmitGlobalBarrier();
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SynchronizeGpu();
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break;
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// DbDataWritebackInvalidate, DbMetadataWritebackInvalidate, CbMetadataWritebackInvalidate.
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case 0x0000002a:
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@@ -1607,6 +1607,145 @@ public:
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order == 2 && gpu_thread != caller_thread && nested_thread == gpu_thread,
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"host command did not run on the GPU thread or nested sync deadlocked");
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{
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const auto make_release_mem = [](uint32_t data_sel, uint32_t interrupt_selector,
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void* destination, uint64_t value) {
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std::array<uint32_t, 8> packet {};
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const auto address = reinterpret_cast<uint64_t>(destination);
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constexpr uint32_t eop_none = 0x28u;
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constexpr uint32_t gcr_gl2_writeback = 1u << 9u;
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packet[0] = KYTY_PM4(8, Pm4::IT_NOP, Pm4::R_RELEASE_MEM);
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packet[1] = eop_none | (gcr_gl2_writeback << 12u);
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packet[2] = (interrupt_selector << 24u) | (data_sel << 29u);
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packet[3] = static_cast<uint32_t>(address);
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packet[4] = static_cast<uint32_t>(address >> 32u);
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packet[5] = static_cast<uint32_t>(value);
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packet[6] = static_cast<uint32_t>(value >> 32u);
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packet[7] = 0x123u;
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return packet;
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};
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vk::SemaphoreTypeCreateInfo timeline_type {};
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timeline_type.sType = vk::StructureType::eSemaphoreTypeCreateInfo;
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timeline_type.semaphoreType = vk::SemaphoreType::eTimeline;
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vk::SemaphoreCreateInfo timeline_create {};
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timeline_create.sType = vk::StructureType::eSemaphoreCreateInfo;
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timeline_create.pNext = &timeline_type;
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vk::Semaphore blocked_timeline = nullptr;
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Require("GpuCommandLane", "blocked timeline create",
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m_runtime_context.device.createSemaphore(
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&timeline_create, nullptr, &blocked_timeline) == vk::Result::eSuccess &&
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blocked_timeline != nullptr,
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"failed to create the blocked GPU timeline");
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constexpr uint64_t release_tick = 1;
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auto& gpu_scheduler = context.GetCommandScheduler();
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auto processor = std::make_unique<CommandProcessor>(context);
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gpu.SendCommandSync([&] {
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SubmitInfo blocked_submit;
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blocked_submit.AddWait(blocked_timeline, release_tick);
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gpu_scheduler.Flush(blocked_submit);
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});
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std::binary_semaphore parser_complete {0};
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alignas(uint64_t) uint64_t interrupt_only_gds_label = UINT64_MAX;
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bool parser_kept_nonblocking_boundaries = false;
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std::jthread no_gpu_wait([&] {
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gpu.SendCommandSync([&] {
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processor->BufferInit();
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const auto tick_before = gpu_scheduler.CurrentTick();
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processor->TriggerEvent(0x16u, 0u);
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auto packet = make_release_mem(0, 0, nullptr, 0);
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Pm4Execution execution;
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const auto result = processor->Process(execution, packet.data(), packet.size());
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processor->IncrementDe();
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const bool cache_and_counter_did_not_submit =
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result == Pm4ProcessResult::Complete &&
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gpu_scheduler.CurrentTick() == tick_before;
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auto gds_interrupt_only =
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make_release_mem(5, 1, &interrupt_only_gds_label, 1ull << 16u);
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Pm4Execution gds_interrupt_execution;
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const auto interrupt_tick = gpu_scheduler.CurrentTick();
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const auto interrupt_result = processor->Process(
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gds_interrupt_execution, gds_interrupt_only.data(), gds_interrupt_only.size());
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parser_kept_nonblocking_boundaries =
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cache_and_counter_did_not_submit &&
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interrupt_result == Pm4ProcessResult::Complete &&
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gpu_scheduler.CurrentTick() == interrupt_tick + 1 &&
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interrupt_only_gds_label == UINT64_MAX;
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});
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parser_complete.release();
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});
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const bool parser_did_not_wait_gpu =
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parser_complete.try_acquire_for(std::chrono::seconds(2));
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vk::SemaphoreSignalInfo signal_info {};
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signal_info.sType = vk::StructureType::eSemaphoreSignalInfo;
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signal_info.semaphore = blocked_timeline;
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signal_info.value = release_tick;
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Require("GpuCommandLane", "blocked timeline signal",
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m_runtime_context.device.signalSemaphore(&signal_info) == vk::Result::eSuccess,
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"failed to release the blocked GPU timeline");
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no_gpu_wait.join();
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gpu.SendCommandSync([&] { gpu_scheduler.Finish(); });
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m_runtime_context.device.destroySemaphore(blocked_timeline, nullptr);
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Require("GpuCommandLane", "nonblocking GPU packets",
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parser_did_not_wait_gpu && parser_kept_nonblocking_boundaries,
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"a cache event, GL2 writeback, DE counter, or interrupt boundary used the wrong "
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"submission behavior");
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alignas(uint64_t) uint64_t release_label = 0;
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alignas(uint64_t) uint64_t gds_label = UINT64_MAX;
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bool release_mem_submission_counts = false;
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gpu.SendCommandSync([&] {
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processor->BufferInit();
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auto immediate = make_release_mem(1, 0, &release_label, 0x11223344u);
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Pm4Execution immediate_execution;
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const auto immediate_tick = gpu_scheduler.CurrentTick();
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const auto immediate_result =
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processor->Process(immediate_execution, immediate.data(), immediate.size());
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const bool immediate_split_once =
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gpu_scheduler.CurrentTick() == immediate_tick + 1;
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auto gds = make_release_mem(5, 0, &gds_label, 1ull << 16u);
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Pm4Execution gds_execution;
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const auto gds_tick = gpu_scheduler.CurrentTick();
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const auto gds_result = processor->Process(gds_execution, gds.data(), gds.size());
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const bool gds_waited_once = gpu_scheduler.CurrentTick() == gds_tick + 1;
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auto interrupt_only = make_release_mem(0, 4, nullptr, 0);
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Pm4Execution interrupt_execution;
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const auto interrupt_tick = gpu_scheduler.CurrentTick();
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const auto interrupt_result = processor->Process(
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interrupt_execution, interrupt_only.data(), interrupt_only.size());
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const bool interrupt_split_once =
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gpu_scheduler.CurrentTick() == interrupt_tick + 1;
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auto gds_interrupt = make_release_mem(5, 2, &gds_label, 1ull << 16u);
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Pm4Execution gds_interrupt_execution;
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const auto gds_interrupt_tick = gpu_scheduler.CurrentTick();
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const auto gds_interrupt_result = processor->Process(
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gds_interrupt_execution, gds_interrupt.data(), gds_interrupt.size());
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const bool gds_interrupt_waited_once =
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gpu_scheduler.CurrentTick() == gds_interrupt_tick + 1;
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release_mem_submission_counts =
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immediate_result == Pm4ProcessResult::Complete && immediate_split_once &&
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gds_result == Pm4ProcessResult::Complete && gds_waited_once &&
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interrupt_result == Pm4ProcessResult::Complete && interrupt_split_once &&
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gds_interrupt_result == Pm4ProcessResult::Complete &&
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gds_interrupt_waited_once;
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});
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gpu.SendCommandSync([&] { gpu_scheduler.Finish(); });
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Require("GpuCommandLane", "RELEASE_MEM submission counts",
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release_mem_submission_counts &&
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static_cast<uint32_t>(release_label) == 0x11223344u &&
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static_cast<uint32_t>(gds_label) == 0,
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"RELEASE_MEM lost its required split/readback or retained a redundant GPU wait");
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}
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alignas(uint32_t) uint32_t packet_marker_a = 0;
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alignas(uint32_t) uint32_t packet_marker_b = 0;
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const auto write_packet = [](uint32_t* packet, uint32_t* destination, uint32_t value) {
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@@ -18420,14 +18559,16 @@ void CheckPm4CeCompletion(RenderContext& renderer) {
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uint32_t suffix = 0;
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const auto address = reinterpret_cast<uint64_t>(&suffix);
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std::array<uint32_t, 7> commands {};
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std::array<uint32_t, 9> commands {};
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commands[0] = 0xc0008600u;
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commands[1] = 1;
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commands[2] = KYTY_PM4(5, Pm4::IT_WRITE_DATA, 0);
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commands[2] = 0xc0008500u;
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commands[3] = 0;
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commands[4] = static_cast<uint32_t>(address);
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commands[5] = static_cast<uint32_t>(address >> 32u);
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commands[6] = 33;
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commands[4] = KYTY_PM4(5, Pm4::IT_WRITE_DATA, 0);
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commands[5] = 0;
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commands[6] = static_cast<uint32_t>(address);
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commands[7] = static_cast<uint32_t>(address >> 32u);
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commands[8] = 33;
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processor.ResetDeCe();
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Pm4Execution execution;
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@@ -18437,11 +18578,30 @@ void CheckPm4CeCompletion(RenderContext& renderer) {
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suffix == 0,
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"DE did not wait for an active CE stream");
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processor.SetCeComplete(true);
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Require("Pm4CeCompletion", "complete",
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std::array<uint32_t, 2> ce_increment {0xc0008400u, 1};
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Pm4Execution ce_execution;
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Require("Pm4CeCompletion", "CE increment",
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processor.Process(ce_execution, ce_increment.data(), ce_increment.size()) ==
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Pm4ProcessResult::Complete,
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"CE counter increment did not complete");
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Require("Pm4CeCompletion", "counter gate",
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processor.Process(execution, commands.data(), commands.size()) ==
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Pm4ProcessResult::Complete &&
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suffix == 33,
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"DE did not resume after CE advanced or failed to increment its counter");
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suffix = 0;
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Pm4Execution balanced_execution;
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Require("Pm4CeCompletion", "balanced wait",
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processor.Process(balanced_execution, commands.data(), commands.size()) ==
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Pm4ProcessResult::Blocked &&
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suffix == 0,
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"balanced CE/DE counters did not gate the next DE packet");
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processor.SetCeComplete(true);
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Require("Pm4CeCompletion", "stream complete",
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processor.Process(balanced_execution, commands.data(), commands.size()) ==
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Pm4ProcessResult::Complete &&
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suffix == 33,
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"DE remained blocked after the CE stream completed");
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std::printf("[host] %-32s ok\n", "Pm4CeCompletion");
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}
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