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https://github.com/KytyPS5/KytyPS5.git
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shader: implement RDNA2 frexp mantissa
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nmzik committed
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1be9568a02
commit
330889e50b
7 files changed
+61
-16
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@@ -567,6 +567,7 @@ std::string OpcodeToString(Opcode opcode) {
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case Opcode::VCvtRpiI32F32: return "v_cvt_rpi_i32_f32";
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case Opcode::VCvtFlrI32F32: return "v_cvt_flr_i32_f32";
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case Opcode::VFrexpExpI32F32: return "v_frexp_exp_i32_f32";
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case Opcode::VFrexpMantF32: return "v_frexp_mant_f32";
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case Opcode::VCvtOffF32I4: return "v_cvt_off_f32_i4";
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case Opcode::VCvtF32Ubyte0: return "v_cvt_f32_ubyte0";
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case Opcode::VCvtF32Ubyte1: return "v_cvt_f32_ubyte1";
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@@ -152,6 +152,7 @@ enum class Opcode {
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VCvtRpiI32F32,
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VCvtFlrI32F32,
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VFrexpExpI32F32,
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VFrexpMantF32,
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VCvtOffF32I4,
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VCvtF32Ubyte0,
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VCvtF32Ubyte1,
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@@ -121,6 +121,7 @@ constexpr OpcodeMap VOP1_OPCODE_LIST[] = {
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{0x39u, Opcode::VFfbhU32},
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{0x3au, Opcode::VFfblB32},
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{0x3fu, Opcode::VFrexpExpI32F32},
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{0x40u, Opcode::VFrexpMantF32},
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{0x42u, Opcode::VMovreldB32},
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{0x43u, Opcode::VMovrelsB32},
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{0x50u, Opcode::VCvtF16U16},
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@@ -170,6 +171,7 @@ constexpr OpcodeMap VOP3_ENCODED_VOP1_OPCODE_LIST[] = {
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{0x39u, Opcode::VFfbhU32},
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{0x3au, Opcode::VFfblB32},
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{0x3fu, Opcode::VFrexpExpI32F32},
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{0x40u, Opcode::VFrexpMantF32},
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{0x42u, Opcode::VMovreldB32},
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{0x43u, Opcode::VMovrelsB32},
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{0x50u, Opcode::VCvtF16U16},
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@@ -413,6 +415,7 @@ bool IsVop1FloatSourceOpcode(Opcode opcode) {
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case Opcode::VCvtRpiI32F32:
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case Opcode::VCvtFlrI32F32:
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case Opcode::VFrexpExpI32F32:
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case Opcode::VFrexpMantF32:
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case Opcode::VCvtF16F32:
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case Opcode::VRcpF32:
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case Opcode::VRcpIflagF32:
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@@ -767,6 +770,7 @@ bool IsVop1FloatResultOpcode(Opcode opcode) {
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case Opcode::VCeilF32:
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case Opcode::VRndneF32:
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case Opcode::VFloorF32:
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case Opcode::VFrexpMantF32:
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case Opcode::VExpF32:
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case Opcode::VLogF32:
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case Opcode::VRsqF32:
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@@ -93,6 +93,26 @@ bool Translator::TranslateFloat16Operation(const IR::Instruction& inst) {
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}
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bool Translator::TranslateFloatOperation(const IR::Instruction& inst) {
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if (inst.op == IR::Opcode::FrexpMantF32) {
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const auto bits = ReadU32(inst.src[0]);
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const auto exponent = IR::U32(
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ir.Emit(IR::ValueOpcode::BitFieldUExtract, {bits, IR::Value(23u), IR::Value(8u)}));
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const auto mantissa = ir.BitwiseAnd(bits, IR::U32(IR::Value(0x007fffffu)));
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const auto sign = ir.BitwiseAnd(bits, IR::U32(IR::Value(0x80000000u)));
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const auto base = ir.BitwiseOr(sign, IR::U32(IR::Value(0x3f000000u)));
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const auto normal = ir.BitwiseOr(base, mantissa);
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const auto msb = IR::U32(ir.Emit(IR::ValueOpcode::FindUMsb32, {mantissa}));
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const auto shift = ir.ISub(IR::U32(IR::Value(23u)), msb);
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const auto fraction =
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ir.BitwiseAnd(ir.ShiftLeftLogical(mantissa, shift), IR::U32(IR::Value(0x007fffffu)));
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const auto subnormal = ir.BitwiseOr(base, fraction);
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const auto zero = ir.IEqual(mantissa, IR::U32(IR::Value(0u)));
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const auto finite = ir.Select(ir.INotEqual(exponent, IR::U32(IR::Value(0u))), normal,
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ir.Select(zero, bits, subnormal));
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const auto result = ir.Select(ir.IEqual(exponent, IR::U32(IR::Value(0xffu))), bits, finite);
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WriteOperand(inst.dst, ir.BitCastF32(result));
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return true;
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}
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IR::ValueOpcode opcode {};
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switch (inst.op) {
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case IR::Opcode::RcpF32: opcode = IR::ValueOpcode::FPRecip32; break;
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@@ -104,6 +104,7 @@ constexpr LowerMap LOWER_OPS[] = {
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{Decoder::Opcode::VCvtRpiI32F32, Opcode::ConvertRoundPlusInfF32ToI32},
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{Decoder::Opcode::VCvtFlrI32F32, Opcode::ConvertFloorF32ToI32},
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{Decoder::Opcode::VFrexpExpI32F32, Opcode::FrexpExpI32F32},
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{Decoder::Opcode::VFrexpMantF32, Opcode::FrexpMantF32},
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{Decoder::Opcode::VCvtOffF32I4, Opcode::ConvertI4ToOffsetF32},
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{Decoder::Opcode::VRcpF32, Opcode::RcpF32},
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{Decoder::Opcode::VRcpIflagF32, Opcode::RcpIflagF32},
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@@ -214,6 +214,7 @@ IR_OPCODE(ConvertF16ToI16, General, Conversion)
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IR_OPCODE(ConvertRoundPlusInfF32ToI32, General, Conversion)
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IR_OPCODE(ConvertFloorF32ToI32, General, Conversion)
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IR_OPCODE(FrexpExpI32F32, General, Conversion)
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IR_OPCODE(FrexpMantF32, General, Float)
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IR_OPCODE(ConvertI4ToOffsetF32, General, Conversion)
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IR_OPCODE(LdexpF32, General, Float)
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IR_OPCODE(PackF32ToF16Rtz, General, Conversion)
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@@ -13527,13 +13527,13 @@ TestCase VectorFloatConversionOps() {
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O::SEndpgm}};
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}
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TestCase VectorFrexpExpI32F32Edges() {
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TestCase VectorFrexpF32Edges() {
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using O = ShaderOpcode;
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const std::vector<u32> inputs = {
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0x00000000u, 0x80000000u, 0x3f000000u, 0xbf800000u,
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0x40800000u, 0xc1000000u, 0x00800000u, 0x007fffffu,
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0x00000001u, 0x7f800000u, 0x7fc00000u,
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0x00000000u, 0x80000000u, 0x3f000000u, 0xbf800000u, 0x40800000u,
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0xc1000000u, 0x00800000u, 0x007fffffu, 0x00000001u, 0x7f800000u,
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0x7fc00000u, 0xff800000u, 0x7fa00001u,
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};
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std::vector<u32> code;
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for (u32 i = 0; i < static_cast<u32>(inputs.size()); i++) {
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@@ -13541,27 +13541,44 @@ TestCase VectorFrexpExpI32F32Edges() {
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AppendBufferLoadDword(&code, i == 3u ? 23u : i, 31);
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}
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for (u32 i = 0; i < static_cast<u32>(inputs.size()); i++) {
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const auto dst = 16u + i;
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if (dst == 19u) {
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const auto exponent_dst = i == 3u ? 19u : 32u + i;
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const auto mantissa_dst = i == 3u ? 21u : 48u + i;
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if (i == 3u) {
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code.push_back(0x7e267ef9u); // captured v_frexp_exp_i32_f32 v19, abs(v23)
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code.push_back(0x00260617u);
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} else {
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code.push_back(EncodeVop1(0x3f, dst, Vgpr(i)));
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code.push_back(EncodeVop1(0x3f, exponent_dst, Vgpr(i)));
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}
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AppendStoreVgpr(&code, dst, i);
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AppendStoreVgpr(&code, exponent_dst, i);
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if (i == 3u) {
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code.push_back(0x7e2a80f9u); // captured v_frexp_mant_f32 v21, abs(v23)
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code.push_back(0x00260617u);
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} else {
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code.push_back(EncodeVop1(0x40, mantissa_dst, Vgpr(i)));
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}
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AppendStoreVgpr(&code, mantissa_dst, inputs.size() + i);
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}
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AppendEnd(&code);
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TestCase test;
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test.name = "VectorFrexpExpI32F32Edges";
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test.name = "VectorFrexpF32Edges";
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test.code = std::move(code);
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test.initial = inputs;
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test.expected = {0u, 0u, 0u, 1u, 3u, 4u,
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0xffffff83u, 0xffffff82u, 0xffffff6cu, 0u, 0u};
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test.opcodes = {O::VMovB32, O::BufferLoadDword, O::VFrexpExpI32F32,
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O::BufferStoreDword, O::SEndpgm};
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test.decoded_counts = {{"v_frexp_exp_i32_f32", inputs.size()}};
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test.required_spirv = {"FindUMsb", "OpBitFieldUExtract"};
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test.initial.resize(inputs.size() * 2u);
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test.expected = {
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0u, 0u, 0u, 1u, 3u,
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4u, 0xffffff83u, 0xffffff82u, 0xffffff6cu, 0u,
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0u, 0u, 0u, 0x00000000u, 0x80000000u,
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0x3f000000u, 0x3f000000u, 0x3f000000u, 0xbf000000u, 0x3f000000u,
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0x3f7ffffeu, 0x3f000000u, 0x7f800000u, 0x7fc00000u, 0xff800000u,
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0x7fa00001u,
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};
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test.opcodes = {O::VMovB32, O::BufferLoadDword, O::VFrexpExpI32F32,
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O::VFrexpMantF32, O::BufferStoreDword, O::SEndpgm};
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test.decoded_counts = {{"v_frexp_exp_i32_f32", inputs.size()},
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{"v_frexp_mant_f32", inputs.size()}};
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test.required_spirv = {"FindUMsb", "OpBitFieldUExtract",
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"OpShiftLeftLogical"};
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return test;
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}
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@@ -17880,7 +17897,7 @@ std::vector<TestCase> MakeCases() {
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AddCase(VectorMinMaxF32NanAndSignedZeroEdges);
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AddCase(VectorMed3F32NanUsesMin3Path);
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AddCase(VectorFloatConversionOps);
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AddCase(VectorFrexpExpI32F32Edges);
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AddCase(VectorFrexpF32Edges);
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AddCase(CvtF32ToIntSaturatesNaNAndOutOfRange);
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AddCase(VectorSpecialF32FlushesDenormalInputs);
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AddCase(VectorRcpIflagF32IntegerReciprocal);
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