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shader: V_CMPX_LT_I16 + fix SDWA with SEXT
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nmzik committed
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17100ec968
commit
bc193f5272
5 files changed
+194
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@@ -384,6 +384,7 @@ enum class Opcode {
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V_CMP_GT_I16,
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V_CMP_NE_I16,
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V_CMP_GE_I16,
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V_CMPX_LT_I16,
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V_CMP_LT_F16,
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V_CMP_EQ_F16,
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V_CMP_LE_F16,
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@@ -239,6 +239,7 @@ constexpr VopcOpcodeInfo VOPC_OPCODE_LIST[] = {
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{0x92u, Opcode::V_CMPX_EQ_I32}, {0x93u, Opcode::V_CMPX_LE_I32},
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{0x94u, Opcode::V_CMPX_GT_I32}, {0x95u, Opcode::V_CMPX_NE_I32},
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{0x96u, Opcode::V_CMPX_GE_I32}, {0x98u, Opcode::V_CMPX_CLASS_F32},
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{0x99u, Opcode::V_CMPX_LT_I16, false},
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{0xa9u, Opcode::V_CMP_LT_U16}, {0xaau, Opcode::V_CMP_EQ_U16},
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{0xabu, Opcode::V_CMP_LE_U16}, {0xacu, Opcode::V_CMP_GT_U16},
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{0xadu, Opcode::V_CMP_NE_U16}, {0xaeu, Opcode::V_CMP_GE_U16},
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@@ -1487,6 +1488,7 @@ bool IsVopcCompareExec(Opcode opcode) {
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case Opcode::V_CMPX_GE_U32:
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case Opcode::V_CMPX_NE_I64:
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case Opcode::V_CMPX_NE_U64:
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case Opcode::V_CMPX_LT_I16:
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case Opcode::V_CMPX_LT_U16:
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case Opcode::V_CMPX_EQ_U16:
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case Opcode::V_CMPX_GT_U16:
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@@ -560,6 +560,12 @@ IR::U32 Translator::ReadU16LaneRaw(const Decoder::Operand& operand, bool high_la
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} else if (operand.sdwa_sel == 4u || operand.sdwa_sel == 5u) {
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offset = operand.sdwa_sel == 5u ? 16u : 0u;
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}
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if (width == 8u && operand.sdwa_sext) {
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// Extend the selected byte into the 16-bit operand before halfword modifiers.
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const auto value = IR::U32(
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ir.Emit(IR::ValueOpcode::BitFieldSExtract, {bits, IR::Value(offset), IR::Value(width)}));
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return ir.BitwiseAnd(value, IR::U32(IR::Value(0xffffu)));
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}
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return IR::U32(
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ir.Emit(IR::ValueOpcode::BitFieldUExtract, {bits, IR::Value(offset), IR::Value(width)}));
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}
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@@ -567,7 +573,7 @@ IR::U32 Translator::ReadU16LaneRaw(const Decoder::Operand& operand, bool high_la
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IR::U32 Translator::ReadU16LaneAsU32(const Decoder::Operand& operand, bool high_lane,
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bool sign_extend) {
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auto value = Read16LaneBits(operand, high_lane);
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if (sign_extend || operand.sdwa_sext) {
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if (sign_extend) {
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value = IR::U32(
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ir.Emit(IR::ValueOpcode::BitFieldSExtract, {value, IR::Value(0u), IR::Value(16u)}));
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}
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@@ -156,6 +156,9 @@ void Translator::EmitVector(const Decoder::Instruction& inst) {
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case O::V_CMP_LT_I16:
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EmitInteger16Compare(inst, IR::ValueOpcode::SLessThan32, true, false);
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return;
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case O::V_CMPX_LT_I16:
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EmitInteger16Compare(inst, IR::ValueOpcode::SLessThan32, true, true);
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return;
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case O::V_CMP_LE_I16:
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EmitInteger16Compare(inst, IR::ValueOpcode::SLessThanEqual32, true, false);
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return;
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@@ -23761,6 +23761,158 @@ TestCase VectorVopcCmpxLtU16CapturedSdwaExecMask() {
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return test;
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}
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TestCase VectorVopcCmpxLtI16CapturedSdwaExecMask() {
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using O = ShaderOpcode;
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enum Encoding { Captured, Compact, Vop3, HighLhs, HighRhs, SdwaOperands };
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struct CompareCase {
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u32 lhs;
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u32 rhs;
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u32 expected_exec;
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Encoding encoding = Captured;
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u32 incoming_exec = 1;
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u32 src0_sel = 6;
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u32 src1_sel = 6;
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u32 src0_sext = 0;
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u32 src1_sext = 0;
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};
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const std::array<CompareCase, 30> cases{{
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{0xffff000eu, 15u, 1}, // Ignore the high half: 14 < 15.
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{0x8000000fu, 15u, 0}, // Equality is false despite a negative high half.
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{0x00000010u, 15u, 0},
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{0x7fff0000u, 15u, 1},
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{0x0000ffffu, 15u, 1}, // Signed -1, not unsigned 65535.
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{0x00008000u, 15u, 1}, // Minimum signed halfword.
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{0x00007fffu, 15u, 0}, // Maximum signed halfword.
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{0x0000fff0u, 15u, 1},
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{0x0000ffffu, 15u, 0, Captured, 0}, // Cannot reactivate an inactive lane.
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{0xffff000fu, 15u, 0, Captured, 0},
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{0x1234ffffu, 0xabcd0000u, 1, Compact}, // -1 < 0.
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{0xffff0000u, 0x0000ffffu, 0, Compact}, // 0 < -1 is false.
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{0xabcd8000u, 0x12347fffu, 1, Vop3},
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{0x12347fffu, 0xabcd8000u, 0, Vop3},
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{0xffff0010u, 15u, 1, HighLhs}, // Select -1 in WORD_1.
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{0x0010ffffu, 15u, 0, HighLhs}, // Select 16, not the negative low half.
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{0x1234fffeu, 0xffff8000u, 1, HighRhs}, // -2 < selected -1.
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{0x1234ffffu, 0xabcd0000u, 1, SdwaOperands, 1, 4, 4, 1, 1},
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{0x12345680u, 0u, 1, SdwaOperands, 1, 0, 6, 1, 0}, // BYTE_0 SEXT: -128.
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{0x1234567fu, 0u, 0, SdwaOperands, 1, 0, 6, 1, 0}, // +127.
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{0x12345680u, 0u, 0, SdwaOperands, 1, 0, 6, 0, 0}, // Without SEXT: +128.
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{0x12348000u, 0u, 1, SdwaOperands, 1, 1, 6, 1, 0},
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{0x12803456u, 0u, 1, SdwaOperands, 1, 2, 6, 1, 0},
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{0x80345678u, 0u, 1, SdwaOperands, 1, 3, 6, 1, 0},
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{0x0000ffffu, 0x12345680u, 0, SdwaOperands, 1, 6, 0, 0, 1}, // -1 < -128 is false.
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{0x0000ff7fu, 0x12345680u, 1, SdwaOperands, 1, 6, 0, 0, 1}, // -129 < -128.
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{0x0000ffffu, 0x12347f00u, 1, SdwaOperands, 1, 6, 1, 0, 1},
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{0u, 0x12803456u, 0, SdwaOperands, 1, 6, 2, 0, 1},
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{0u, 0x80345678u, 0, SdwaOperands, 1, 6, 3, 0, 1},
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{0xff000001u, 0x000100ffu, 1, SdwaOperands, 1, 3, 2, 1, 1},
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}};
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constexpr u32 vcc_lo = 0x76543210u;
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constexpr u32 vcc_hi = 0x89abcdefu;
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TestCase test;
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test.name = "VectorVopcCmpxLtI16CapturedSdwaExecMask";
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for (const auto &entry : cases) {
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test.initial.push_back(entry.lhs);
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}
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test.expected = test.initial;
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auto &code = test.code;
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for (u32 i = 0; i < cases.size(); ++i) {
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const auto &entry = cases[i];
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AppendVMovU32(&code, 30, i * 4u);
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AppendBufferLoadDword(&code, 1, 30); // Runtime input prevents constant folding.
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AppendVMovU32(&code, 2, entry.rhs);
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AppendSMovLiteral(&code, 106, vcc_lo);
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AppendSMovLiteral(&code, 107, vcc_hi);
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code.push_back(EncodeSMovB32(126, InlineU32(entry.incoming_exec)));
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switch (entry.encoding) {
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case Compact: code.push_back(0x7d320501u); break;
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case Vop3: code.insert(code.end(), {0xd499007eu, 0x00020501u}); break;
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case HighLhs: code.insert(code.end(), {0x7d331ef9u, 0x86050001u}); break;
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case HighRhs:
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code.push_back(EncodeVopc(0x99u, 249u, 2u));
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code.push_back(EncodeVopcSdwa(1u, 0u, 0u, 6u, 5u));
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break;
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case SdwaOperands:
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code.push_back(EncodeVopc(0x99u, 249u, 2u));
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code.push_back(EncodeVopcSdwa(1u, 0u, 0u, entry.src0_sel, entry.src1_sel,
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entry.src0_sext, entry.src1_sext));
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break;
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default: code.insert(code.end(), {0x7d331ef9u, 0x86060001u}); break;
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}
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code.push_back(EncodeSMovB32(20, 126)); // Snapshot EXEC before restoring it.
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code.push_back(EncodeSMovB32(21, 127));
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code.push_back(EncodeSMovB32(126, InlineU32(1)));
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const u32 out = static_cast<u32>(cases.size()) + i * 4u;
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AppendStoreSgprPair(&code, 20, out);
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AppendStoreSgprPair(&code, 106, out + 2u); // CMPX preserves both VCC halves.
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test.expected.insert(test.expected.end(),
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{entry.expected_exec, 0u, vcc_lo, vcc_hi});
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}
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AppendEnd(&code);
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test.opcodes = {O::V_MOV_B32, O::S_MOV_B32, O::BUFFER_LOAD_DWORD,
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O::V_CMPX_LT_I16, O::BUFFER_STORE_DWORD, O::S_ENDPGM};
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test.decoded_counts = {{"V_CMPX_LT_I16", cases.size()}};
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test.required_spirv = {"OpSLessThan", "OpBitFieldSExtract"};
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return test;
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}
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TestCase VectorVopcCmpxLtI16WaveMasks(u32 wave_size) {
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using O = ShaderOpcode;
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constexpr u32 marker = 0xfeedabcdu;
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constexpr u32 vcc_lo = 0x01234567u;
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constexpr u32 vcc_hi = 0x89abcdefu;
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constexpr u32 expected_exec_lo = 0xaaaaaaaau;
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const u32 expected_exec_hi = wave_size == 64u ? 0x33333333u : 0u;
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TestCase test;
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test.name = wave_size == 32u ? "VectorVopcCmpxLtI16Wave32Masks"
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: "VectorVopcCmpxLtI16Wave64Masks";
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test.initial.assign(6u * wave_size, 0xdeadbeefu);
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constexpr u32 inputs[] = {0xffff000eu, 0x0000ffffu, 0x8000000fu, 0x12348000u};
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for (u32 lane = 0; lane < wave_size; ++lane) {
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test.initial[lane] = inputs[lane % 4u];
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}
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test.expected = test.initial;
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for (u32 lane = 0; lane < wave_size; ++lane) {
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test.expected[wave_size + lane] = expected_exec_lo;
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test.expected[2u * wave_size + lane] = expected_exec_hi;
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test.expected[3u * wave_size + lane] = vcc_lo;
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test.expected[4u * wave_size + lane] = vcc_hi;
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const u32 mask = lane < 32u ? expected_exec_lo : expected_exec_hi;
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if ((mask & (1u << (lane % 32u))) != 0u) {
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test.expected[5u * wave_size + lane] = marker;
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}
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}
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auto &code = test.code;
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code.push_back(EncodeVop2(0x1a, 30, InlineU32(2), 0));
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AppendBufferLoadDword(&code, 1, 30);
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AppendVMovLiteral(&code, 4, marker);
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code.push_back(EncodeSop1(0x04, 10, 126)); // Save the full incoming EXEC.
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AppendSMovLiteral(&code, 106, vcc_lo);
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AppendSMovLiteral(&code, 107, vcc_hi);
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AppendSMovLiteral(&code, 126, 0xeeeeeeeeu);
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AppendSMovLiteral(&code, 127, 0x77777777u);
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code.insert(code.end(), {0x7d331ef9u, 0x86060001u});
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code.push_back(EncodeSMovB32(20, 126));
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code.push_back(EncodeSMovB32(21, 127));
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AppendStoreVgprAtLaneDwordOffset(&code, 4, 0, 5u * wave_size);
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code.push_back(EncodeSop1(0x04, 126, 10)); // Restore lanes to inspect the raw masks.
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AppendStoreSgprAtLaneDwordOffset(&code, 20, 0, wave_size);
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AppendStoreSgprAtLaneDwordOffset(&code, 21, 0, 2u * wave_size);
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AppendStoreSgprAtLaneDwordOffset(&code, 106, 0, 3u * wave_size);
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AppendStoreSgprAtLaneDwordOffset(&code, 107, 0, 4u * wave_size);
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AppendEnd(&code);
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test.compute_info.threads_num[0] = wave_size;
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test.compute_info.threads_num[1] = test.compute_info.threads_num[2] = 1;
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test.compute_info.thread_ids_num = 1;
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test.compute_info.wave_size = wave_size;
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test.has_compute_info = true;
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test.opcodes = {O::V_MOV_B32, O::S_MOV_B32, O::S_MOV_B64, O::V_LSHLREV_B32,
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O::V_ADD_NC_U32, O::BUFFER_LOAD_DWORD, O::V_CMPX_LT_I16,
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O::BUFFER_STORE_DWORD, O::S_ENDPGM};
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test.required_spirv = {"OpSLessThan", "OpBitFieldSExtract"};
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return test;
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}
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TestCase VectorVopcCmpxEqU16SdwaCompactVop3ExecMask() {
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using O = ShaderOpcode;
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struct CompareCase {
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@@ -23768,9 +23920,9 @@ TestCase VectorVopcCmpxEqU16SdwaCompactVop3ExecMask() {
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u32 rhs;
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u32 incoming_exec;
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u32 expected_exec;
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u32 encoding = 0; // 0: SDWA, 1: compact, 2: VOP3, 3: SDWA sign-extend.
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u32 encoding = 0; // SDWA, compact, VOP3, sign-extended words/bytes.
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};
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const std::array<CompareCase, 12> cases{{
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const std::array<CompareCase, 16> cases{{
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{0x12340000u, 0x56780000u, 1, 1}, // Equal low half; ignore high half.
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{0xffff0001u, 0xabcd0001u, 1, 1},
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{0x00000000u, 0x12340000u, 1, 1},
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@@ -23783,6 +23935,10 @@ TestCase VectorVopcCmpxEqU16SdwaCompactVop3ExecMask() {
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{0x00008000u, 0x0000ffffu, 1, 0, 2},
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{0x0001ffffu, 0x12340001u, 1, 0, 3}, // Sign-extended low halves differ.
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{0x00000001u, 0x00010001u, 0, 0}, // CMPX cannot reactivate an inactive lane.
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{0x12345680u, 0x0000ff80u, 1, 1, 4}, // SEXT BYTE_0 is unsigned U16 0xff80.
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{0x123456ffu, 0x0000ffffu, 1, 1, 4},
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{0x0000ff80u, 0x12348000u, 1, 1, 5}, // SEXT BYTE_1 on src1.
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{0x1234ffffu, 0x5678ffffu, 1, 1, 6}, // SEXT WORD_0 versus DWORD low half.
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}};
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constexpr u32 vcc_hi = 0x89abcdefu;
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TestCase test;
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@@ -23807,6 +23963,18 @@ TestCase VectorVopcCmpxEqU16SdwaCompactVop3ExecMask() {
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code.push_back(EncodeVopc(0xba, 249u, 1u));
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code.push_back(EncodeVopcSdwa(0u, 0u, 0u, 6u, 6u, 1u, 1u));
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break;
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case 4:
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code.push_back(EncodeVopc(0xba, 249u, 1u));
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code.push_back(EncodeVopcSdwa(0u, 0u, 0u, 0u, 6u, 1u, 0u));
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break;
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case 5:
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code.push_back(EncodeVopc(0xba, 249u, 1u));
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code.push_back(EncodeVopcSdwa(0u, 0u, 0u, 6u, 1u, 0u, 1u));
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break;
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case 6:
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code.push_back(EncodeVopc(0xba, 249u, 1u));
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code.push_back(EncodeVopcSdwa(0u, 0u, 0u, 4u, 6u, 1u, 0u));
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break;
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default:
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code.push_back(EncodeVopc(0xba, 249u, 1u));
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code.push_back(EncodeVopcSdwa(0u));
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@@ -30594,6 +30762,10 @@ std::vector<TestCase> MakeCases() {
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AddCase(VectorVopcSdwaCmpxWritesExecMask);
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AddCase(VectorVopcCmpxGtU16CapturedSdwaExecMask);
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AddCase(VectorVopcCmpxLtU16CapturedSdwaExecMask);
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AddCase(VectorVopcCmpxLtI16CapturedSdwaExecMask);
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for (u32 wave_size : {32u, 64u}) {
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cases.push_back(VectorVopcCmpxLtI16WaveMasks(wave_size));
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}
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AddCase(VectorVopcCmpxEqU16SdwaCompactVop3ExecMask);
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AddCase(VectorVopcCmpNgtF16CapturedSdwaAndEdges);
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AddCase(VectorVopcCmpNltF16CapturedSdwaAndEdges);
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@@ -35515,6 +35687,13 @@ int main(int argc, char **argv) {
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RunCase(&vulkan, VectorVopcCmpxEqU16SdwaCompactVop3ExecMask());
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return 0;
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}
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if (argc == 2 && std::strcmp(argv[1], "--cmpx-lt-i16-only") == 0) {
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VulkanHarness vulkan;
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RunCase(&vulkan, VectorVopcCmpxLtI16CapturedSdwaExecMask());
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RunCase(&vulkan, VectorVopcCmpxLtI16WaveMasks(32));
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RunCase(&vulkan, VectorVopcCmpxLtI16WaveMasks(64));
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return 0;
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}
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if (argc == 2 && std::strcmp(argv[1], "--cmpx-lt-u16-only") == 0) {
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VulkanHarness vulkan;
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RunCase(&vulkan, VectorVopcCmpxLtU16CapturedSdwaExecMask());
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